Input driven self-clocked dynamic comparator

A self-clocked dynamic comparator, comprising:

• a latch configured to receive an input voltage (VIN), a reference voltage (VREF) and a clocking (CLKsf) signal, and configured to output a first rail-to-rail output (OUT+) signal and a second rail-to-rail output (OUT−) signal;
• a first pre-amplifier (PRE-AMP) configured to output a first enable (TRI) signal based on a comparison between the VIN and VREF-Δv;
• and
• a first AND gate configured to receive the first TRI signal and one of the OUT− signal, and configured to output the CLKsf signal;
• a second PRE-AMP configured to output a second TRI signal based on a comparison between the VIN and VREF+Δv;
• and
• a second AND gate configured to receive the second TRI signal and the OUT+ signal, and configured to output the CLKsf signal;
• wherein cycles of the CLKsf signal cause the latch to dissipate energy.

A method for operating a self-clocked dynamic comparator, the method comprising:

• comparing an input voltage (VIN) and an adjusted reference voltage (adjusted VREF) by a pre-amplifier (PRE-AMP);
• outputting an enable (TRI) signal by the PRE-AMP, wherein the TRI signal is based on a comparison between the VIN and the adjusted VREF;
• comparing the TRI signal and one of a first rail-to-rail output (OUT+) signal and a second rail-to-rail output (OUT−) signal by an AND gate;
• outputting a clocking (CLKsf) signal by the AND gate;
• receiving the VIN, a reference voltage (VREF) and the CLKsf signal by a latch;
• and
• outputting the OUT+ signal and the OUT− signal by the latch,
• wherein cycles of the CLKsf signal cause the latch to dissipate energy.