# US 11,909,399 B2 · System and semiconductor device therein

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- Number: US 11,909,399 B2
- Document ID: US11909399B2
- Status: Granted
- Kind: B2
- Application number: 17/828,834
- Filed: 2022-05-31
- Published: 2023-11-30
- Granted: 2024-02-20
- Earliest claimed: 2022-05-31
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Tsung-Che Lu; Chin-Ming Fu; Chih-Hsien Chang
- Web page: https://patentgrep.com/patent/US11909399B2

## CPC

- H03K 5/01: Shaping pulses (discrimination against noise or interference H03K5/125)
- H03K 5/14: by the use of delay lines (H03K5/133 takes precedence)
- G06F 1/06: Clock generators producing several clock signals {(G06F1/08 - G06F1/14 take precedence)}
- H03K 3/037: Bistable circuits
- H03K 19/20: characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence)
- H03K 19/0016: {by using a control or a clock signal, e.g. in order to apply power supply}
- H03K 2005/00013: {Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A system includes a measuring device, a processing device and a signal generating device. The measuring device is configured to measure a voltage difference between a first node and a second node. The processing device is coupled between the first node and the second node. The signal generating device is configured to provide a first clock signal to the processing device to adjust the voltage difference, configured to generate the first clock signal according to a first enable signal and a second clock signal, and configured to align an edge of the first enable signal with an edge of the second clock signal. A method and a device are also disclosed herein.

## Claims

### Claim 1

A system, comprising:
a measuring device configured to measure a voltage difference between a first node and a second node;
a processing device coupled between the first node and the second node; and
a signal generating device configured to provide a first clock signal to the processing device to adjust the voltage difference, configured to generate the first clock signal according to a first enable signal and a second clock signal, and configured to align an edge of the first enable signal with an edge of the second clock signal.

### Claim 2 (depends on 1)

The system of claim 1, wherein the signal generating device comprises:
a delaying circuit configured to adjust the first enable signal according to a voltage level of the second clock signal at a moment of the edge of the first enable signal.

### Claim 3 (depends on 2)

The system of claim 2, wherein the signal generating device further comprises:
a dividing circuit configured to divide a frequency of the second clock signal, to generate a second enable signal,
wherein the delaying circuit is further configured to delay the second enable signal according to the voltage level to generate the first enable signal.

### Claim 4 (depends on 1)

The system of claim 1, wherein the signal generating device is further configured to adjust the first enable signal according to a feedback signal, and
the signal generating device comprises:
a detecting circuit configured detect a voltage level of the second clock signal at a moment of the edge of the first enable signal, to generate the feedback signal corresponding to the voltage level.

### Claim 5 (depends on 4)

The system of claim 4, wherein the detecting circuit comprises:
a flip flop configured to be triggered by the edge of the first enable signal to generate the feedback signal corresponding to the voltage level.

### Claim 6 (depends on 1)

The system of claim 1, wherein the signal generating device further comprises:
a controlling circuit configured to compare a voltage level of the second clock signal at a moment of the edge of the first enable signal with a first voltage threshold level, and configured to delay the edge of the first enable signal when the voltage level does not meet the first threshold voltage level.

### Claim 7 (depends on 6)

The system of claim 6, wherein the controlling circuit is further configured to accumulate logic values corresponding to the voltage level,
in response to the voltage level has a first voltage level, each of the logic values has a first value,
in response to the voltage level has a second voltage level, each of the logic values has a second value, and
in response to the voltage level has a third voltage level between the first voltage level and the second voltage level, each of a first part of the logic values has the first value, and each of a second part of the logic values has the second value.

### Claim 8 (depends on 6)

The system of claim 6, wherein the controlling circuit is further configured to delay the edge of the first enable signal until the voltage level is higher than the first threshold voltage level.

### Claim 9 (depends on 8)

The system of claim 8, wherein the controlling circuit is further configured to delay the edge of the first enable signal until the voltage level is lower than a second threshold voltage level which is lower than the first threshold voltage level, before the voltage level is higher than the first threshold voltage level.

### Claim 10 (depends on 6)

The system of claim 6, wherein the signal generating device comprises:
a plurality of delaying units configured to be turned on in order until the voltage level meets the first threshold voltage level, each of the plurality of delaying units being configured to delay the first enable signal when turned on.

### Claim 11

A method, comprising:
delaying, by a delaying circuit, a first enable signal by a first delay time period to generate a second enable signal;
generating, by a detecting circuit, a feedback signal according to a voltage level of a first clock signal at a moment of an edge of the second enable signal; and
adjusting, by a controlling circuit, the first delay time period according to the feedback signal, until the edge of the second enable signal is aligned with an edge of the first clock signal.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
generating a second clock signal according to the second enable signal and the first clock signal;
applying the second clock signal to adjust a voltage difference; and
measuring the voltage difference when the second clock signal oscillates.

### Claim 13 (depends on 11)

The method of claim 11, wherein adjusting the first delay time period comprises:
sensing the feedback signal to generate a plurality of first logic values;
accumulate the plurality of first logic values to generate an accumulated value;
comparing the accumulated value with a first threshold value;
in response to the accumulated value being larger than the first threshold value, increasing the first delay time period by a second delay time period; and
after increasing the first delay time period by the second delay time period, resetting the accumulated value.

### Claim 14 (depends on 13)

The method of claim 13, wherein adjusting the first delay time period further comprises:
after increasing the first delay time period by the second delay time period, in response to the accumulated value being larger than the first threshold value, increasing the first delay time period by the second delay time period.

### Claim 15 (depends on 13)

The method of claim 13, wherein adjusting the first delay time period further comprises:
after the accumulated value being smaller than or equal to the first threshold value, sensing the feedback signal to generate a plurality of second logic values;
accumulate the plurality of second logic values to generate the accumulated value;
comparing the accumulated value with a second threshold value larger than the first threshold value; and
in response to the accumulated value being smaller than the second threshold value, increasing the first delay time period by the second delay time period.

### Claim 16

A device, comprising:
a dividing circuit configured to divide a first clock signal to generate a first enable signal;
a delaying circuit configured to delay the first enable signal according to a feedback signal, to generate a second enable signal;
a gating circuit configured to receive the second enable signal and be triggered by the first clock signal; and
a detecting circuit configured to receive the first clock signal and be triggered by the second enable signal, to generate the feedback signal.

### Claim 17 (depends on 16)

The device of claim 16, further comprising:
a controlling circuit configured to accumulate logic values of the feedback signal to generate a controlling signal,
wherein the delaying circuit is further configured to adjust the second enable signal according to the controlling signal.

### Claim 18 (depends on 17)

The device of claim 17, wherein the delaying circuit comprises:
a first delaying unit configured to increase a delay time period between the second enable signal and the first enable signal, when an accumulated value accumulated from the logic values is larger than a first threshold value; and
a second delaying unit configured to increase the delay time period, when the accumulated value is larger than the first threshold value, after the delay time period is increased by the first delaying unit.

### Claim 19 (depends on 18)

The device of claim 18, wherein the delaying circuit further comprises:
a third delaying unit configured to increase the delay time period, when the accumulated value is smaller than a second threshold value larger than the first threshold value, after the delay time period is increased by the second delaying unit.

### Claim 20 (depends on 17)

The device of claim 17, further comprising:
a logic circuit configured to control the gating circuit according to a selecting signal,
wherein the gating circuit is further configured to provide a second clock signal to the controlling circuit,
in response to the selecting signal having a first logic value, the second clock signal oscillates, and
in response to the selecting signal having a second logic value different from the first logic value, the second clock signal does not oscillate.