# US 11,909,397 B2 · Detecting device and semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,909,397 B2 - Document ID: US11909397B2 - Status: Granted - Kind: B2 - Application number: 17/286,091 - Filed: 2019-10-17 - Published: 2021-11-18 - Granted: 2024-02-20 - Earliest claimed: 2018-10-25 - Assignees: Semiconductor Energy Laboratory Co., Ltd. - Applicants: Semiconductor Energy Laboratory Co., Ltd. - Inventors: Shintaro Harada; Takayuki Ikeda - Web page: https://patentgrep.com/patent/US11909397B2 ## CPC - H03K 3/037: Bistable circuits - H03K 3/356026: {with synchronous operation (H03K3/356034, H03K3/356052 take precedence)} - A61B 5/0022: {Monitoring a patient using a global network, e.g. telephone networks, internet} - A61B 5/01: Measuring temperature of body parts {; Diagnostic temperature sensing, e.g. for malignant or inflamed tissue} (clinical contact thermometers G01K13/20) - A61B 5/024: Measuring pulse rate or heart rate - A61B 5/11: Measuring movement of the entire body or parts thereof, e.g. head or hand tremor or mobility of a limb {(A61B5/1038 takes precedence; motion detection to correct for motion artifacts in physiological signals A61B5/721)} - A61B 5/14532: {for measuring glucose, e.g. by tissue impedance measurement} - A61B 5/363: Detecting tachycardia or bradycardia - A61B 5/681: {Wristwatch-type devices} - G01R 31/3644: {Constructional arrangements} - G01R 31/3835: involving only voltage measurements - G06F 1/04: Generating or distributing clock signals or signals derived directly therefrom - G06F 1/06: Clock generators producing several clock signals {(G06F1/08 - G06F1/14 take precedence)} - G06F 1/163: {Wearable computers, e.g. on a belt} - G06F 1/28: Supervision thereof, e.g. detecting power-supply failure by out of limits supervision - G06F 1/3234: Power saving characterised by the action undertaken - G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence) - H03K 3/356078: {with synchronous operation} - H03K 23/40: Gating or clocking signals applied to all stages, i.e. synchronous counters {(H03K23/74 - H03K23/84 take precedence)} - H10D 30/67: Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)} - H10D 84/0126: {the components including insulated gates, e.g. IGFETs} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/83: of only insulated-gate FETs [IGFET] - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - A61B: DIAGNOSIS; SURGERY; IDENTIFICATION (usefulness limited to only animals A61D) - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract The power of a semiconductor device is reduced. The semiconductor device includes a latch circuit composed of a dynamic circuit. The latch circuit includes a first circuit having a decoding function, a plurality of capacitors, a plurality of clock input terminals, a signal input terminal, a first output terminal, and a second output terminal. In a period during which “H” is supplied to a first clock signal, the potential of the first capacitor is updated on the basis of the results of decoding performed by the first circuit. In a period during which “H” is supplied to a second clock signal, the potential of the second capacitor is updated on the basis of the potential of the first capacitor, and the potential of the second capacitor is supplied as a first output signal to the first output terminal. In a period during which “H” is supplied to a third clock signal, the potential of the third capacitor is updated on the basis of the potential of the second capacitor, and the potential of the third capacitor is supplied as a second output signal to the second output terminal. ## Claims ### Claim 1 A semiconductor device comprising a latch circuit composed of a dynamic circuit, wherein the latch circuit comprises a first circuit, first to third capacitors, first to third clock input terminals, a signal input terminal, a first output terminal, and a second output terminal, wherein the first circuit is configured to perform decoding, wherein the first to third clock input terminals are configured to be supplied with first to third clock signals, respectively, wherein, in a period during which an “H” signal is supplied to the first clock signal: the first circuit is configured to be supplied with a plurality of input signals through the signal input terminal; and a potential of the first capacitor is configured to be updated on the basis of a result of decoding performed by the first circuit, wherein, in a period during which the “H” signal is supplied to the second clock signal: a potential of the second capacitor is configured to be updated on the basis of the potential of the first capacitor; and the first output terminal is configured to be supplied with the potential of the second capacitor as a first output signal, and wherein, in a period during which the “H” signal is supplied to the third clock signal: a potential of the third capacitor is configured to be updated on the basis of the potential of the second capacitor; and the second output terminal is configured to be supplied with the potential of the third capacitor as a second output signal. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the latch circuit comprises fourth to sixth clock input terminals, wherein fourth to sixth clock signals are sequentially supplied to the fourth to sixth clock input terminals, wherein the first capacitor is precharged in a period during which the “H” signal is supplied to the fourth clock signal, wherein the second capacitor is precharged in a period during which the “H” signal is supplied to the fifth clock signal, and wherein the third capacitor is precharged in a period during which the “H” signal is supplied to the sixth clock signal. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein the latch circuit comprises a second circuit, wherein the second circuit generates a seventh clock signal and an eighth clock signal from the second clock signal supplied to the second clock input terminal, wherein the latch circuit is configured to latch a result of decoding the input signal and outputting the latch result to the first output signal in a period during which the “H” signal is supplied to the seventh clock signal, and wherein, in a period during which the “H” signal is supplied to the eighth clock signal: the second capacitor is precharged by supply of the fifth clock signal to the fifth clock input terminal; a potential of the precharged second capacitor is output as the “H” signal to the first output signal when the first output signal is the “H” signal; the potential of the second capacitor is discharged by the second output signal when the first output signal is an “L” signal; and the potential of the second capacitor is output as the “L” signal to the first output signal. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, comprising a plurality of the latch circuits which are cascade-connected, wherein the cascade-connected latch circuits are configured as a counter circuit. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, wherein the latch circuit comprises first to fifth transistors, wherein the first clock input terminal is electrically connected to a gate of the first transistor, wherein the third clock input terminal is electrically connected to a gate of the third transistor, wherein the fifth clock input terminal is electrically connected to a gate of the fifth transistor, wherein one electrode of the second capacitor is electrically connected to a gate of the fourth transistor, wherein one electrode of the third capacitor is electrically connected to the gate of the fifth transistor, wherein the first to fifth transistors each comprise a metal oxide in a semiconductor layer, wherein the first to fifth transistors each comprise a back gate, and wherein a potential supplied to the back gates of the first to third transistors is different from a potential supplied to the back gates of the fourth and fifth transistors. ### Claim 6 (depends on 4) A detecting device comprising the semiconductor device according to claim 4, a detecting circuit, and a battery, wherein an output signal of the semiconductor device is supplied to the detecting circuit, and wherein the detecting circuit uses the output signal as a monitor cycle for monitoring an output potential of the battery.