# US 11,909,394 B2 · Level shifter circuit

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- Number: US 11,909,394 B2
- Document ID: US11909394B2
- Status: Granted
- Kind: B2
- Application number: 17/756,676
- Filed: 2020-11-13
- Published: 2022-12-29
- Granted: 2024-02-20
- Earliest claimed: 2019-12-09
- Assignees: Sony Semiconductor Solutions Corporation
- Applicants: Sony Semiconductor Solutions Corporation
- Inventors: Yoshikatsu Jingu
- Web page: https://patentgrep.com/patent/US11909394B2

## CPC

- H03K 19/018521: {of complementary type, e.g. CMOS}
- G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters}
- H03K 3/037: Bistable circuits
- H03K 19/018528: {with at least one differential stage}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

Provided is a level shifter circuit that changes a voltage of a high-frequency input signal to output. Provided is a level shifter circuit provided with a first input terminal and a second input terminal to each of which an input signal having a level between a first potential level and a first reference potential level is input, a first output terminal and a second output terminal from each of which an output signal having a level between a second potential level higher than the first potential level and a second reference potential level is output, a second potential supply node that supplies a voltage at the second potential level, a reference potential supply node that supplies a voltage at the second reference potential level, first and second impedance elements, first to fourth transistors, and first and second nodes, in which each of the first impedance element and the second impedance element includes at least three terminals.

## Claims

### Claim 1

A level shifter circuit, comprising:
a first input terminal and a second input terminal, wherein each of the first input terminal and the second input terminal is configured to receive an input signal having a level between a first potential level and a first reference potential level;
a first output terminal and a second output terminal, wherein each of the first output terminal and the second output terminal is configured to output an output signal having a level between a second potential level higher than the first potential level and a second reference potential level;
a second potential supply node configured to supply a voltage at the second potential level;
a first reference potential supply node configured to supply a voltage at the second reference potential level;
a second reference potential supply node;
a third reference potential supply node;
a first direct current power supply;
a second direct current power supply;
a first resistance element;
a second resistance element;
a first impedance element and a second impedance element;
a first transistor having a first conductivity type;
a second transistor having a second conductivity type;
a third transistor having the first conductivity type;
a fourth transistor having the second conductivity type; and
a first node and a second node, wherein
a control terminal of the second transistor is connected to the first input terminal,
a control terminal of the fourth transistor is connected to the second input terminal,
the first node is connected to the first output terminal,
the second node is connected to the second output terminal,
the first transistor is connected between the second potential supply node and the first node,
the second transistor is connected between the first reference potential supply node and the first node,
the third transistor is connected between the second potential supply node and the second node,
the fourth transistor is connected between the first reference potential supply node and the second node,
each of the first impedance element and the second impedance element includes at least three terminals and at least one capacitance element,
a first terminal of the first impedance element is connected to the control terminal of the second transistor,
a second terminal of the first impedance element is connected to the second node,
a third terminal of the first impedance element is connected to a control terminal of the first transistor,
a first terminal of the second impedance element is connected to the control terminal of the fourth transistor,
a second terminal of the second impedance element is connected to the first node,
a third terminal of the second impedance element is connected to a control terminal of the third transistor,
the first direct current power supply and the first resistance element are connected in series in this order from a side of the second reference potential supply node,
the first direct current power supply and the first resistance element are between the second reference potential supply node and the control terminal of the first transistor,
the third terminal of the first impedance element is connected between the first resistance element and the control terminal of the first transistor,
the second direct current power supply and the second resistance element are connected in series in this order from a side of the third reference potential supply node,
the second direct current power supply and the second resistance element are between the third reference potential supply node and the control terminal of the third transistor, and
the third terminal of the second impedance element is connected between the second resistance element and the control terminal of the third transistor.

### Claim 2 (depends on 1)

The level shifter circuit according to claim 1, wherein
each of the first transistor and the third transistor is a P-channel field effect transistor, and
each of the second transistor and the fourth transistor is an N-channel field effect transistor.

### Claim 3 (depends on 1)

The level shifter circuit according to claim 1, wherein each of the first impedance element and the second impedance element further includes at least one resistance element.

### Claim 4 (depends on 3)

The level shifter circuit according to claim 3, wherein in each of the first impedance element and the second impedance element, the at least one resistance element is connected between the first terminal and the second terminal.

### Claim 5 (depends on 3)

The level shifter circuit according to claim 3, wherein in each of the first impedance element and the second impedance element, the at least one resistance element is connected between the first terminal and the third terminal.

### Claim 6 (depends on 1)

The level shifter circuit according to claim 1, wherein in each of the first impedance element and the second impedance element, the at least one capacitance element is connected between the first terminal and the second terminal.

### Claim 7 (depends on 1)

The level shifter circuit according to claim 1, wherein in each of the first impedance element and the second impedance element,
at least one resistance element is connected between the first terminal and the second terminal, and
the at least one capacitance element is not connected between the second terminal and the third terminal.

### Claim 8 (depends on 7)

The level shifter circuit according to claim 7, wherein in each of the first impedance element and the second impedance element, the at least one resistance element and the at least one capacitance element are connected in series between the first terminal and the second terminal.

### Claim 9 (depends on 1)

The level shifter circuit according to claim 1, further comprising a first inverter and a second inverter,
wherein the first inverter and the second inverter are connected in series between the first input terminal and the control terminal of the fourth transistor.