# US 11,909,388 B2 · Terminal resistance circuit, chip and chip communication device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,909,388 B2 - Document ID: US11909388B2 - Status: Granted - Kind: B2 - Application number: 17/732,564 - Filed: 2022-04-29 - Published: 2022-09-08 - Granted: 2024-02-20 - Earliest claimed: 2020-12-09 - Assignees: Shenzhen Pango Microsystems Co., Ltd - Applicants: Shenzhen Pango Microsystems Co., Ltd - Inventors: Qianwen Zhang; Aimei Liang; Changqing Wen; Qiwei Wang - Web page: https://patentgrep.com/patent/US11909388B2 ## CPC - H03K 17/6872: {using complementary field-effect transistors} - G06F 13/20: for access to input/output bus - H03K 17/223: {in field-effect transistor switches} - H03K 17/6874: {in a symmetrical configuration} - H03K 19/173: using elementary logic circuits as components - G06F 2213/40: Bus coupling - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A terminal resistance circuit, a chip and a chip communication device are provided. The terminal resistance circuit can be used for a high-speed differential I/O pair and includes two resistance circuits and a control circuit. An end of the two resistance circuits connected in series is connected to a first interface and another end is connected to a second interface. A conductor wire connected between the two resistance circuits has a target node thereon. The two resistance circuits are symmetrically arranged relative to the target node. The control circuit is connected to the two resistance circuits individually and used to control the two resistance circuits each to be in a turn-off state during powering-on of the chip. An abnormal operation caused by a short circuit between two interfaces of a I/O pair during the powering-on of the chip is avoided and the working stability of the chip is improved. ## Claims ### Claim 1 A terminal resistance circuit, adapted for a high-speed differential input/output (I/O) pair of a chip; wherein the high-speed differential I/O pair comprises a first interface and a second interface, and the terminal resistance circuit comprises: two resistance circuits, wherein an end of the two resistance circuits connected in series is electrically connected to the first interface, another end of the two resistance circuits connected in series is electrically connected to the second interface, a conductor wire connected between the two resistance circuits has a target node thereon, and the two resistance circuits are symmetrically arranged with respect to the target node; and a control circuit, electrically connected to the two resistance circuits individually and configured to control the two resistance circuits each to be in a turn-off state during powering-on of the chip. ### Claim 2 (depends on 1) The terminal resistance circuit according to claim 1, wherein each of the two resistance circuits comprises a resistance element, a first switch element and a second switch element; a first end of the resistance element is electrically connected to the target node through the first switch element, and a second end of the resistance element is electrically connected to one of the first interface and the second interface; and wherein the second switch element is electrically connected to the first end of the resistance element and the target node. ### Claim 3 (depends on 2) The terminal resistance circuit according to claim 2, wherein the first switch element comprises a first metal-oxide-semiconductor (MOS) transistor, a source of the first MOS transistor is electrically connected to the first end of the resistance element, a drain of the first MOS transistor is electrically connected to the target node, a gate of the first MOS transistor is electrically connected to the control circuit, and the first MOS transistor is a P-type MOS transistor. ### Claim 4 (depends on 3) The terminal resistance circuit according to claim 3, wherein the control circuit comprises a first P-type MOS transistor, a second P-type MOS transistor, a first N-type MOS transistor, a second N-type MOS transistor and a third N-type MOS transistor; wherein a source of the first P-type MOS transistor is electrically connected to the first end of the resistance element, a drain of the first P-type MOS transistor is electrically connected to the gate of the first MOS transistor, and a gate of the first P-type MOS transistor is connected to a first designated control port; wherein a source of the second P-type MOS transistor is electrically connected to the first end of the resistance element, a drain of the second P-type MOS transistor is electrically connected to the gate of the first MOS transistor, and a gate of the second P-type MOS transistor is connected to a second designated control port; wherein a drain of the first N-type MOS transistor is electrically connected to the gate of the first MOS transistor, a source of the first N-type MOS transistor is electrically connected to a drain of the second N-type MOS transistor, and a gate of the first N-type MOS transistor is electrically connected to the first designated control port; wherein a source of the second N-type MOS transistor is electrically connected to a drain of the third N-type MOS transistor, and a gate of the second N-type MOS transistor is electrically connected to the second designated control port; and wherein a source of the third N-type MOS transistor is grounded, and a gate of the third N-type MOS transistor is electrically connected to a third designated control port. ### Claim 5 (depends on 2) The terminal resistance circuit according to claim 2, wherein the second switch element comprises a second MOS transistor, a source of the second MOS transistor is electrically connected to the target node, a drain of the second MOS transistor is electrically connected to the first end of the resistance element, a gate of the second MOS transistor is electrically connected to a third designated control port, and the second MOS transistor is a N-type MOS transistor. ### Claim 6 (depends on 2) The terminal resistance circuit according to claim 2, wherein each of the two resistance circuits further comprises a third switch element, and the third switch element is electrically connected to the first switch element and the target node. ### Claim 7 (depends on 6) The terminal resistance circuit according to claim 6, wherein the third switch element comprises a third MOS transistor, a source of the third MOS transistor is electrically connected to a drain of a first MOS transistor of the first switch element, a drain of the third MOS transistor is electrically connected to the target node, a gate of the third MOS transistor is electrically connected to a fourth designated control port, and the third MOS transistor is a P-type MOS transistor. ### Claim 8 (depends on 1) The terminal resistance circuit according to claim 1, wherein the terminal resistance circuit further comprises: a filter capacitor element, an end of the filter capacitor element being electrically connected to the target node, and another end of the filter capacitor element being grounded. ### Claim 9 A chip, comprising: a field programmable gate array (FPGA) chip body and a terminal resistance circuit; wherein a high-speed differential I/O pair of the FPGA chip body comprises a first interface and a second interface; and wherein the terminal resistance circuit comprises: two resistance circuits connected in series, wherein an end of the series-connected two resistance circuits is electrically connected to the first interface, another end of the series-connected two resistance circuits is electrically connected to the second interface, a wire connected between the two resistance circuits has a target node thereon, and the two resistance circuits are symmetrically arranged with respect to the target node; and a control circuit, electrically connected to the two resistance circuits and configured to control the two resistance circuits each to be in a turn-off state during powering-on of the chip. ### Claim 10 (depends on 9) The chip according to claim 9, wherein each of the two resistance circuits comprises a resistance element, a first switch element and a second switch element; a first end of the resistance element is electrically connected to the target node through the first switch element, and a second end of the resistance element is electrically connected to one of the first interface and the second interface; and wherein the second switch element is electrically connected to the first end of the resistance element and the target node. ### Claim 11 (depends on 10) The chip according to claim 10, wherein the first switch element comprises a first metal-oxide-semiconductor (MOS) transistor, a source of the first MOS transistor is electrically connected to the first end of the resistance element, a drain of the first MOS transistor is electrically connected to the target node, a gate of the first MOS transistor is electrically connected to the control circuit, and the first MOS transistor is a P-type MOS transistor; and wherein the second switch element comprises a second MOS transistor, a source of the second MOS transistor is electrically connected to the target node, a drain of the second MOS transistor is electrically connected to the first end of the resistance element, a gate of the second MOS transistor is electrically connected to a third designated control port, and the second MOS transistor is a N-type MOS transistor. ### Claim 12 (depends on 10) The chip according to claim 10, wherein each of the two resistance circuits further comprises a third switch element, and the third switch element is electrically connected to the first switch element and the target node. ### Claim 13 (depends on 12) The chip according to claim 12, wherein the third switch element comprises a third MOS transistor, a source of the third MOS transistor is electrically connected to the first switch element, a drain of the third MOS transistor is electrically connected to the target node, a gate of the third MOS transistor is electrically connected to a fourth designated control port, and the third MOS transistor is a P-type MOS transistor. ### Claim 14 (depends on 10) The chip according to claim 10, wherein the control circuit comprises a first P-type MOS transistor, a second P-type MOS transistor, a first N-type MOS transistor, a second N-type MOS transistor and a third N-type MOS transistor; wherein a source of the first P-type MOS transistor is electrically connected to the first end of the resistance element, a drain of the first P-type MOS transistor is electrically connected to the first switch element, and a gate of the first P-type MOS transistor is connected to a first designated control port; wherein a source of the second P-type MOS transistor is electrically connected to the first end of the resistance element, a drain of the second P-type MOS transistor is electrically connected to the first switch element, and a gate of the second P-type MOS transistor is connected to a second designated control port; wherein a drain of the first N-type MOS transistor is electrically connected to the first switch element, a source of the first N-type MOS transistor is electrically connected to a drain of the second N-type MOS transistor, and a gate of the first N-type MOS transistor is electrically connected to the first designated control port; wherein a source of the second N-type MOS transistor is electrically connected to a drain of the third N-type MOS transistor, and a gate of the second N-type MOS transistor is electrically connected to the second designated control port; and wherein a source of the third N-type MOS transistor is grounded, and a gate of the third N-type MOS transistor is electrically connected to a third designated control port. ### Claim 15 (depends on 9) The chip according to claim 9, wherein the terminal resistance circuit further comprises: a filter capacitor element, an end of the filter capacitor element being electrically connected to the target node, and another end of the filter capacitor element being grounded. ### Claim 16 A chip communication device, comprising: a first FPGA chip, a second FPGA chip, a first transmission line, a second transmission line and three terminal resistance circuits; wherein the three terminal resistance circuits comprise a first terminal resistance circuit, a second terminal resistance circuit and a third terminal resistance circuit; a high-speed differential I/O pair of the first FPGA chip comprises a first port and a second port, and a high-speed differential I/O pair of the second FPGA chip comprises a third port and a fourth port; wherein the first port of the first FPGA chip is electrically connected to the third port of the second FPGA chip through the first transmission line, and the second port of the first FPGA chip is electrically connected to the fourth port of the second FPGA chip through the second transmission line; wherein the first terminal resistance circuit is integrated in the first FPGA chip; wherein the second terminal resistance circuit is arranged outside the second FPGA chip; wherein the third terminal resistance circuit is integrated in the second FPGA chip; wherein each of the first through third terminal resistance circuits comprises: resistance circuits connected in series, wherein a wire connected between the resistance circuits has a target node thereon; and a control circuit, electrically connected to the resistance circuits and configured to control the resistance circuits each to be in a turn-off state during powering-on of the chip; wherein an end of the series-connected resistance circuits of the first terminal resistance circuit is electrically connected to the first port, another end of the series-connected resistance circuits of the first terminal resistance circuit is electrically connected to the second port, and wherein an end of the series-connected resistance circuits of the second terminal resistance circuit is electrically connected to the third port, another end of the series-connected resistance circuits of the second terminal resistance circuit is electrically connected to the fourth port; and wherein an end of the series-connected resistance circuits of the third terminal resistance circuit is electrically connected to the third port, another end of the series-connected resistance circuits of the third terminal resistance circuit is electrically connected to the fourth port. ### Claim 17 (depends on 16) The chip communication device according to claim 16, wherein each of the resistance circuits comprises a resistance element, a first switch element and a second switch element; wherein a first end of the resistance element is electrically connected to the target node through the first switch element, the second switch element is electrically connected to the first end of the resistance element and the target node; wherein a second end of the resistance element of the first terminal resistance circuit is electrically connected to one of the first port and the second port; wherein a second end of the resistance element of the second terminal resistance circuit is electrically connected to one of the third port and the fourth port; and wherein a second end of the resistance element of the third terminal resistance circuit is electrically connected to one of the third port and the fourth port. ### Claim 18 (depends on 17) The chip communication device according to claim 17, wherein each of the resistance circuits further comprises a third switch element, and the third switch element is electrically connected to the first switch element and the target node. ### Claim 19 (depends on 17) The chip communication device according to claim 17, wherein the control circuit comprises a first P-type MOS transistor, a second P-type MOS transistor, a first N-type MOS transistor, a second N-type MOS transistor and a third N-type MOS transistor; wherein a source of the first P-type MOS transistor is electrically connected to the first end of the resistance element, a drain of the first P-type MOS transistor is electrically connected to the first switch element, and a gate of the first P-type MOS transistor is connected to a first designated control port; wherein a source of the second P-type MOS transistor is electrically connected to the first end of the resistance element, a drain of the second P-type MOS transistor is electrically connected to the first switch element, and a gate of the second P-type MOS transistor is connected to a second designated control port; wherein a drain of the first N-type MOS transistor is electrically connected to the first switch element, a source of the first N-type MOS transistor is electrically connected to a drain of the second N-type MOS transistor, and a gate of the first N-type MOS transistor is electrically connected to the first designated control port; wherein a source of the second N-type MOS transistor is electrically connected to a drain of the third N-type MOS transistor, and a gate of the second N-type MOS transistor is electrically connected to the second designated control port; and wherein a source of the third N-type MOS transistor is grounded, and a gate of the third N-type MOS transistor is electrically connected to a third designated control port. ### Claim 20 (depends on 16) The chip communication device according to claim 16, wherein each of the first through third terminal resistance circuits further comprises: a filter capacitor element, an end of the filter capacitor element being electrically connected to the target node, and another end of the filter capacitor element being grounded.