# US 11,909,387 B2 · Microphone with slew rate controlled buffer > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,909,387 B2 - Document ID: US11909387B2 - Status: Granted - Kind: B2 - Application number: 17/691,717 - Filed: 2022-03-10 - Published: 2022-10-20 - Granted: 2024-02-20 - Earliest claimed: 2021-03-17 - Assignees: Knowles Electronics, LLC - Applicants: Knowles Electronics, LLC - Inventors: Satya Sai Evani; Sudheer Gutta; Sreenath Pariyarath; Gururaj Ghorpade; Sruthi Panangavil - Web page: https://patentgrep.com/patent/US11909387B2 ## CPC - H03K 17/6872: {using complementary field-effect transistors} - H04R 3/00: Circuits for transducers (arrangements for producing a reverberation or echo sound G10K15/08; amplifiers H03F) - H04R 2203/00: Details of circuits for transducers, loudspeakers or microphones covered by H04R3/00 but not provided for in any of its subgroups - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H04R: LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; ELECTRIC HEARING AIDS; PUBLIC ADDRESS SYSTEMS (producing sounds with frequency not determined by supply frequency G10K) ## Abstract A digital microphone or other sensor assembly includes a transducer and an electrical circuit including a slew-rate controlled output buffer configured to reduce propagation delay and maintain output rise and fall time independent of PVT variation and load capacitance. In some embodiments, the portions of the output buffer are selectably disabled to reduce power consumption without adversely substantially increasing propagation delay. ## Claims ### Claim 1 A digital sensor assembly comprising: a transducer configured to generate an analog signal responsive to a sensed environmental condition; an analog-to-digital converter (ADC) having an input coupled to the transducer; and a slew-rate controlled output buffer having an input coupled to an output of the ADC, the slew-rate controlled output buffer comprising: a first current sink circuit; an output driver comprising a first driver coupled to the first current sink circuit; and a first feedback capacitor selectably coupled between a low impedance node of the first current sink circuit and an output node of the output driver when the first current sink circuit is enabled, wherein the first current sink circuit discharges the first driver gate when the first driver needs to be turned ON. ### Claim 2 (depends on 1) The digital sensor of claim 1, the first current sink circuit is a first cascode current sink circuit comprising a drain node coupled to a first gate of the first driver and to a current source circuit, the first cascode current sink circuit comprising a source node selectably coupled to the first feedback capacitor when the first current sink circuit is enabled. ### Claim 3 (depends on 1) The digital sensor of claim 1, the slew-rate controlled output buffer further comprising a second current sink circuit selectably coupled to the first feedback capacitor when the first current sink circuit is disabled, wherein the second current sink circuit maintains charge on the first feedback capacitor when the first current sink circuit is disabled. ### Claim 4 (depends on 1) The digital sensor of claim 1, the slew-rate controlled output buffer further comprising: a first current source circuit; the output driver further comprising a second driver coupled to the first driver and the first current source circuit, the first driver and the second driver are complementary devices; and a second feedback capacitor coupled to the output node of the output driver and selectably coupled to a low impedance node of the first current source circuit when the first current source circuit is enabled, wherein the first current source circuit charges the second driver gate when the second driver needs to be turned ON. ### Claim 5 (depends on 4) The digital sensor of claim 4, the slew-rate controlled output buffer further comprising: a second current sink circuit selectably coupled to the first feedback capacitor when the first current sink circuit is disabled, wherein the second current sink circuit maintains charge on the first feedback capacitor when the first current sink circuit is disabled; and a second current source circuit selectably coupled to the second feedback capacitor when the first current source circuit is disabled, wherein the second current source circuit maintains charge on the second feedback capacitor when the first current source circuit is disabled. ### Claim 6 (depends on 5) The digital sensor of claim 5, the first current sink circuit is a first cascode current sink circuit comprising a drain node coupled to a first gate of the first driver and to a current source, the first cascode current sink circuit comprising a source node selectably coupled to the first feedback capacitor, wherein the current source enables bi-directional slew-rate control during signal transition between low and high at the output node, the second current sink circuit is a second cascode current sink circuit having a source node selectably coupled to the first feedback capacitor opposite the output node, wherein the second current sink circuit maintains charge on the first feedback capacitor when data on the output node is low or impedance is high, the first current source circuit is a first cascode current source circuit comprising a drain node coupled to a second gate of the second driver, the first cascode current source circuit comprising a source node selectably coupled to the second feedback capacitor, and the second current source circuit is a second cascode current source circuit having a source node selectably coupled to the second feedback capacitor opposite the output node, wherein the second cascode current source circuit maintains charge on the second feedback capacitor when data on the output node is high or impedance is high. ### Claim 7 (depends on 6) The digital sensor of claim 6, wherein a gate of the first cascode current sink circuit is coupled to a gate of the second cascode current sink circuit, and a gate of the first cascode current source circuit is coupled to a gate of the second cascode current source circuit. ### Claim 8 (depends on 5) The digital sensor of claim 5, the slew-rate controlled output buffer further comprising a pre-driver coupled to the output driver and configured to: enable the first current sink circuit and connect it to the first feedback capacitor when the first transistor needs to be enabled; disable the first current sink circuit and connect the second current sink circuit to the first feedback capacitor, and pullup a gate of the first driver when the first transistor needs to be disabled; enable the first current source circuit and connect it to the second feedback capacitor when the second transistor needs to be enabled; and disable the first current source circuit connect second current source circuit to the second feedback capacitor and pulldown a gate of the second driver when the second transistor needs to be disabled. ### Claim 9 (depends on 4) The digital sensor of claim 4, the output driver is a push-pull CMOS driver wherein the first transistor is a PMOS transistor and the second transistor is an NMOS transistor. ### Claim 10 An electrical circuit for a digital sensor assembly, comprising: a slew-rate controlled output buffer having an input connectable to a digital circuit of a digital sensor assembly, the slew-rate controlled output buffer comprising: a first current sink circuit; an output driver comprising a first driver coupled to the first current sink circuit; and a first feedback capacitor selectably coupled between a low impedance node of the first current sink circuit and an output node of the output driver when the first current sink circuit is enabled, wherein the first current sink circuit discharges the first driver gate when the first driver needs to be enabled. ### Claim 11 (depends on 10) The electrical circuit of claim 10, the first current sink circuit is a first cascode current sink circuit comprising a drain node coupled to a first gate of the first driver and to a current source circuit, the first cascode current sink circuit comprising a source node selectably coupled to the first feedback capacitor when the first current sink circuit is enabled. ### Claim 12 (depends on 10) The electrical circuit of claim 10, the slew-rate controlled output buffer further comprising a second current sink circuit selectably coupled to the first feedback capacitor when the first current sink circuit is disabled, wherein the second current sink circuit maintains charge on the first feedback capacitor when the first current sink circuit is disabled. ### Claim 13 (depends on 10) The electrical circuit of claim 10, the slew-rate controlled output buffer further comprising: a first current source circuit; the output driver further comprising a second driver coupled to the first driver and the first current source circuit, the first driver and the second driver are complementary devices; and a second feedback capacitor coupled to the output node of the output driver and selectably coupled to a low impedance node of the first current source circuit when the first current source circuit is enabled, wherein the first current source circuit charges the second driver gate when the second driver needs to be enabled. ### Claim 14 (depends on 13) The electrical circuit of claim 13, the slew-rate controlled output buffer further comprising: a second current sink circuit selectably coupled to the first feedback capacitor when the first current sink circuit is disabled, wherein the second current sink circuit maintains charge on the first feedback capacitor when the first current sink circuit is disabled; and a second current source circuit selectably coupled to the second feedback capacitor when the first current source circuit is disabled, wherein the second current source circuit maintains charge on the second feedback capacitor when the first current source circuit is disabled. ### Claim 15 (depends on 14) The electrical circuit of claim 14, the first current sink circuit is a first cascode current sink circuit comprising a drain node coupled to a first gate of the first driver and to a current source, the first cascode current sink circuit comprising a source node selectably coupled to the first feedback capacitor, wherein the current source enables bi-directional slew-rate control during signal transition between low and high at the output node, the second current sink circuit is a second cascode current sink circuit having a source node selectably coupled to the first feedback capacitor opposite the output node, wherein the second current sink circuit maintains charge on the first feedback capacitor when data on the output node is low or impedance is high, the first current source circuit is a first cascode current source circuit comprising a drain node coupled to a second gate of the second driver, the first cascode current source circuit comprising a source node selectably coupled to the second feedback capacitor, and the second current source circuit is a second cascode current source circuit having a source node selectably coupled to the second feedback capacitor opposite the output node, wherein the second cascode current source circuit maintains charge on the second feedback capacitor when data on the output node is high or impedance is high. ### Claim 16 (depends on 15) The electrical circuit of claim 15, wherein a gate of the first cascode current sink circuit is coupled to a gate of the second cascode current sink circuit, and a gate of the first cascode current source circuit is coupled to a gate of the second cascode current source circuit. ### Claim 17 (depends on 14) The electrical circuit of claim 14, the slew-rate controlled output buffer further comprising a pre-driver coupled to the output driver and configured to: enable the first current sink circuit and connect it to the first feedback capacitor when the first transistor needs to be enabled; disable the first current sink circuit and connect the second current sink circuit to the first feedback capacitor, and pullup a gate of the first driver when the first transistor needs to be disabled; enable the first current source circuit and connect it to the second feedback capacitor when the second transistor needs to be enabled; and disable the first current source circuit connect second current source circuit to the second feedback capacitor and pulldown a gate of the second driver when the second transistor needs to be disabled. ### Claim 18 (depends on 13) The digital sensor of claim 13, the output driver is a push-pull CMOS driver wherein the first transistor is a PMOS transistor and the second transistor is an NMOS transistor. ### Claim 19 A method of operating a digital sensor assembly having a slew-rate controlled output driver, the method comprising: generating an electrical signal representative of a condition sensed by a transducer of the digital sensor assembly; providing an output signal, based on the electrical signal, at an output node of slew-rate controlled output driver; selectably coupling a feedback capacitor between a low impedance source of a current sink and the output node when the current sink is enabled, discharging the output driver gate via a drain of the current sink when the feedback capacitor is coupled between the source of the current sink and the output node. ### Claim 20 (depends on 19) The method of claim 19, further comprising selectably coupling the feedback capacitor to a second current sink circuit when the first current sink circuit is disabled, wherein the second current sink circuit maintains charge on the feedback capacitor when the first current sink circuit is disabled.