# US 11,909,384 B2 · Direct-drive D-mode GaN half-bridge power module

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- Number: US 11,909,384 B2
- Document ID: US11909384B2
- Status: Granted
- Kind: B2
- Application number: 17/741,813
- Filed: 2022-05-11
- Published: 2023-11-16
- Granted: 2024-02-20
- Earliest claimed: 2022-05-11
- Assignees: GaN Systems Inc.
- Applicants: GaN Systems Inc.
- Inventors: Di Chen
- Web page: https://patentgrep.com/patent/US11909384B2

## CPC

- H03K 17/223: {in field-effect transistor switches}
- H02H 3/243: {for DC systems}
- H02M 1/081: {wherein the phase of the control voltage is adjustable with reference to the AC source}
- H02M 1/32: Means for protecting converters other than automatic disconnection
- H02M 1/36: Means for starting or stopping converters
- H03K 17/08142: {in field-effect transistor switches}
- H03K 17/687: the devices being field-effect transistors
- H02M 1/0006: {Arrangements for supplying an adequate voltage to the control circuit of converters}
- H02M 7/5387: in a bridge configuration
- H03K 2017/6875: {using self-conductive, depletion FETs}
- H03K 2217/0063: High side switches, i.e. the higher potential [DC] or life wire [AC] being directly connected to the switch and not via the load
- H03K 2217/0072: Low side switches, i.e. the lower potential [DC] or neutral wire [AC] being directly connected to the switch and not via the load
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H02H: EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS (indicating or signalling undesired working conditions G01R, e.g. G01R31/00, G08B; locating faults along lines G01R31/08; emergency protective devices H01H)
- H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P)

## Abstract

A protected direct-drive depletion-mode (D-mode) GaN semiconductor half-bridge power module is disclosed. Applications include high power inverter applications, such as 100 kW to 200 kW electric vehicle traction inverters, and other motor drives. The high-side switch is a normally-on D-mode GaN semiconductor power switch Q1 in series with a normally-off LV Si MOSFET power switch M1 and the low-side switch is a normally on D-mode GaN semiconductor power switch Q2. The gates of both Q1 and Q2 are directly driven. M1 in series with Q1 provides a high-side switch which is a normally-off device for start-up and fail-safe protection. M1 may also be used for current sensing and overcurrent protection. For example, a control circuit determines an operational mode of M1 responsive to a UVLO signal and a voltage sense signal indicative of an overcurrent event. Examples of single phase and three-phase half-bridge modules and driver circuits are described.

## Claims

### Claim 1

A direct drive D-mode half-bridge power module comprising a high-side switch and a low-side switch connected in series, wherein the high-side switch is a D-mode normally-on GaN transistor switch (Q1) in series with an E-mode normally-off Si MOSFET switch (M1) and the low-side switch is a D-mode normally-on GaN transistor switch (Q2), wherein gates of the D-mode normally-on GaN transistor switches Q1 and Q2 are directly driven, and the gate of E-mode normally-off Si MOSFET M1 is directly driven by a control signal, wherein M1 acts as a protection FET to hold the high-side switch in an off-state during start-up and during a fault condition.

### Claim 2 (depends on 1)

The direct drive D-mode half-bridge power module of claim 1, comprising a control circuit which determines the operational mode of M1 responsive to an undervoltage lock-out (UVLO) signal and a voltage sense signal indicative of an overcurrent event.

### Claim 3 (depends on 2)

The direct drive D-mode half-bridge power module of claim 2, wherein the control circuit operates so that: M1 is OFF during start-up until UVLO is off, M1 is ON for normal operation; M1 is turned-off during a fault condition if UVLO is turned-on; and if overcurrent protection (OCP) is triggered, M1 is ON and Q1 and Q2 are turned-off.

### Claim 4 (depends on 1)

A traction inverter comprising a multi-phase motor driver, wherein each phase leg comprises a half-bridge module as defined in claim 1.

### Claim 5 (depends on 1)

A method of operation of a half-bridge module as defined in claim 1, wherein a control circuit is configured to determine an operational mode of M1 responsive to an undervoltage lock-out (UVLO) signal and a voltage sense signal indicative of an overcurrent event, the control circuit operating so that: M1 is OFF during start-up until UVLO is off; M1 is ON for normal operation; M1 is turned-off during a fault condition if UVLO is turned-on; and if overcurrent protection (OCP) is triggered, M1 is ON and Q1 and Q2 are turned-off.

### Claim 6

A power semiconductor switching device comprising:
a high-side switch and a low-side switch connected in series in a half-bridge configuration, between a high voltage DC bus and a low voltage DC bus, the high side switch being connected to the low side switch at a switching node, wherein:
the high-side switch is a normally-off switch wherein a first normally-on GaN transistor switch (Q1) is connected in series with a normally-off Si MOSFET switch (M1), the source of Q1 being connected to the drain of M1;
the low side switch is a normally-on switch, comprising a second normally-on GaN transistor switch (Q2);
wherein gates of the D-mode normally-on GaN transistor switches Q1 or Q2 are directly driven, and the gate of the E-mode normally-off Si MOSFET M1 is directly driven by a control circuit, wherein M1 acts as a protection FET to hold the high-side switch in an off-state during start-up and during a fault condition; and
the control circuit is configured to determine an operational mode of M1 responsive to an undervoltage lock-out (UVLO) signal and a voltage sense signal indicative of an overcurrent event, the control circuit operating so that: M1 is OFF during start-up until UVLO is off; M1 is ON for normal operation; M1 is turned-off during a fault condition if UVLO is turned-on; and if overcurrent protection (OCP) is triggered, M1 is ON and Q1 and Q2 are turned-off.

### Claim 7

A power semiconductor switching device comprising:
a high-side switch and a low-side switch connected in series in a half-bridge configuration, between a high voltage DC bus and a low voltage DC bus, the high side switch being connected to the low side switch at a switching node, wherein
the high-side switch is a normally-off switch wherein a first normally-on GaN transistor switch (Q1) is connected in series with a normally-off Si MOSFET switch (M1), the source of Q1 being connected to the drain of M1;
the low side switch is a normally-on switch, comprising a second normally-on GaN transitory switch (Q2); and
Q1 has a source, a drain and a gate, wherein the drain of Q1 is connected to the high voltage DC bus and the source of Q1 is connected to a drain of M1, and the gate of Q1 is connected to a first gate drive terminal for directly driving the gate of Q1; the source of M1 is connected to the switching node, a gate of M1 is connected to an enable (control) terminal for directly driving the gate of the M1; a high-side ground terminal is connected to the source of M1; and a voltage sense terminal is connected to a common point between the source of Q1 and the drain of M1; and
Q2 has a source, a drain and a gate, the drain of Q2 is connected to the switching node and the source of Q2 is connected to the low voltage DC bus, and the gate of Q2 is connected to a second gate drive terminal for directly driving the gate of Q2; and a low-side ground terminal is connected to the source of Q2.

### Claim 8 (depends on 7)

The power semiconductor switching device of claim 7 wherein: M1 acts as a protection FET to hold the high-side switch in an off-state during start-up and a fault condition.

### Claim 9 (depends on 7)

The power semiconductor switching device of claim 7, wherein:
Q1 comprises a plurality of GaN transistors connected in parallel;
M1 comprises a plurality of Si MOSFETs connected in parallel;
Q2 comprises a plurality of GaN transistors connected in parallel.

### Claim 10 (depends on 7)

The power semiconductor switching device of claim 7, wherein:
Q1 comprises a plurality of GaN HEMTs connected in parallel;
M1 comprises a plurality of Si MOSFET connected in parallel;
Q2 comprises a plurality of GaN HEMTs connected in parallel.

### Claim 11 (depends on 6)

The power semiconductor switching device of claim 6 wherein:
Q1 comprises a plurality of GaN transistors connected in parallel;
M1 comprises a plurality of Si MOSFETs connected in parallel;
Q2 comprises a plurality of GaN transistors connected in parallel.

### Claim 12

A power semiconductor switching device comprising:
a high-side switch and a low-side switch connected in series in a half-bridge configuration, between a high voltage DC bus and a low voltage DC bus, the high side switch being connected to the low side switch at a switching node, wherein:
the high-side switch is a normally-off switch wherein a first normally-on GaN transistor switch (Q1) is connected in series with a normally-off Si MOSFET switch (M1), the source of Q1 being connected to the drain of M1; and
the low side switch is a normally-on switch, comprising a second normally-on GaN transistor switch (Q2);
and
a half-bridge driver circuit comprising:
a high-side driver for directly driving a gate of Q1;
a low-side driver for directly driving a gate of Q2;
wherein the high-side driver and the low-side driver are driven by PWM input signals INH and INL respectively; and
a control circuit for driving M1, wherein the control circuit comprises a gate driver for providing an enable (control) signal for directly driving the gate of M1 in response to a gate input signal PGOOD,
the control circuit having a voltage sense input Vsen from a voltage sense terminal connected to a node between the source of Q1 and the drain of M1,
circuitry for receiving an undervoltage lock-out (UVLO) signal, and determining a power status and operational mode for M1,
circuitry for comparing the voltage sense input Vsen to a reference overcurrent protection (OCP) limit voltage VOCP_limit, wherein said enable signal provides that
M1 is OFF during start-up until UVLO is off;
M1 is ON for normal operation;
M1 is turned-off during a fault condition if UVLO is turned-on;
and
if OCP is triggered, M1 is ON and Q1 and Q2 are turned-off.

### Claim 13 (depends on 12)

The power semiconductor switching device of claim 12 comprising:
a high-side switch and a low-side switch connected in series in a half-bridge configuration, between a high voltage DC bus (rail) and a low voltage DC bus (rail), the high side switch being connected to the low side switch at a switching node, wherein:
the high-side switch is a normally-off switch wherein a first normally-on GaN transistor switch (Q1) is connected in series with a normally-off Si MOSFET switch (M1); and
the low side switch is a normally-on switch, comprising a second normally-on GaN transistor switch (Q2); wherein:
Q1 has a source, a drain and a gate, wherein the drain of Q1 is connected to the high voltage DC bus and the source of Q1 is connected to a drain of M1, and the gate of Q1 is connected to a first gate drive terminal for directly driving the gate of Q1; the source of M1 is connected to the switching node, a gate of M1 is connected to an enable (control) terminal for directly driving the gate of the M1; a high-side ground terminal is connected to the source of M1; and a voltage sense terminal is connected a common point between the source of Q1 and the drain of M1; and
Q2 has a source, a drain and a gate, the drain of Q2 is connected to the switching node and the source of Q2 is connected to the low voltage DC bus, and the gate of Q2 is connected to a second gate drive terminal for directly driving the gate of Q2; and a low-side ground terminal is connected to the source of Q2;
a half-bridge driver circuit comprising:
a high-side driver for directly driving a gate of Q1;
a low-side driver for directly driving a gate of Q2;
wherein the high-side driver and the low-side driver are driven by PWM input signals INH and INL respectively; and
a control circuit for driving M1, wherein the control circuit comprises a gate driver for providing an enable (control) signal for directly driving the gate of M1 in response to a gate input signal PGOOD,
a voltage sense input Vsen from a voltage sense terminal connected to a node between the source of Q1 and the drain of M1,
a UVLO signal input, and circuitry for determining a power status and operational mode for M1,
circuitry for comparing the voltage sense input Vsen to a reference OCP limit voltage VOCP_limit and triggering OCP if Vsen exceeds the OCP limit voltage;
wherein said enable signal provides that
M1 is OFF during start-up until UVLO is off;
M1 is ON for normal operation;
M1 is turned-off during a fault condition if UVLO is turned-on;
and
if OCP is triggered, M1 is ON and Q1 and Q2 are turned-off.