# US 11,909,315 B2 · Switching regulator and controller circuit and control method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,909,315 B2 - Document ID: US11909315B2 - Status: Granted - Kind: B2 - Application number: 17/567,129 - Filed: 2022-01-02 - Published: 2022-07-21 - Granted: 2024-02-20 - Earliest claimed: 2021-01-15 - Assignees: Richtek Technology Corporation - Applicants: Richtek Technology Corporation - Inventors: Yung-Chun Chuang; Huan-Chien Yang - Web page: https://patentgrep.com/patent/US11909315B2 ## CPC - H02M 3/158: including plural semiconductor devices as final control devices for a single load - H02M 1/0025: {Arrangements for modifying reference values, feedback values or error values in the control loop of a converter} - H02M 3/156: with automatic control of output voltage or current, e.g. switching regulators - H02M 3/1566: {with means for compensating against rapid load changes, e.g. with auxiliary current source, with dual mode control or with inductance variation} - Y02B 70/10: Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) - Y02B: CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS ## Abstract A switching regulator includes a power stage circuit and a controller circuit. The controller circuit includes a first amplification circuit, a second amplification circuit, a ramp signal generation circuit, and a comparator. The first amplification circuit generates an amplification signal according to a difference between a low-pass filtered signal and a feedback signal. The second amplification circuit generates an adjustment signal according to a difference between the feedback signal and a fast response signal. The comparator generates a pulse width modulation signal according to a difference between the amplification signal and a ramp signal to generate a switch control signal. The adjustment signal adaptively adjusts the amplification signal or the ramp signal. The low-pass filtered signal is related to a signal generated by filtering out higher frequency part of the reference signal, and the reference signal is related to a dynamic change of a target level of the output voltage. ## Claims ### Claim 1 A switching regulator, comprising: a power stage circuit, which includes an inductor and at least one power switch; wherein the at least one power switch is coupled to the inductor, and is configured to operate according to a switch control signal, to control a conduction status of the inductor, so as to convert an input voltage to an output voltage; and a controller circuit, which is coupled to the power stage circuit, and is configured to operably generate the switch control signal according to a feedback signal and a reference signal, wherein the feedback signal is related to the output voltage and the reference signal is related to a dynamic change of a target level of the output voltage, wherein the controller circuit includes: a first amplification circuit, which is configured to operably generate an amplification signal according to a difference between a low-pass filtered signal and the feedback signal, wherein the low-pass filtered signal is related to a signal generated by low-pass filtering the reference signal based on a first predetermined bandwidth; a second amplification circuit, which is configured to operably generate an adjustment signal according to a difference between the feedback signal and a fast response signal; a ramp signal generation circuit, which is configured to operably generate a ramp signal according to a clock signal; and a comparator, which is configured to operably compare the amplification signal and the ramp signal, to generate a pulse width modulation (PWM) signal, wherein the controller circuit generates the switch control signal according to the PWM signal; wherein the adjustment signal is configured to operably adaptively adjust the amplification signal or the ramp signal, so as to reduce a response time or to mitigate or avoid an overshoot or an undershoot of the output voltage; wherein a voltage level of the fast response signal is between a voltage level of the low-pass filtered signal and a voltage level of the reference signal. ### Claim 2 (depends on 1) The switching regulator of claim 1, wherein the controller circuit further includes a first low-pass filter, which is configured to operably generate the low-pass filtered signal by low-pass filtering the reference signal based on the first predetermined bandwidth. ### Claim 3 (depends on 2) The switching regulator of claim 2, wherein the controller circuit further includes a fast response signal generation circuit, which is configured to operably perform a linear weighting operation on the low-pass filtered signal and the reference signal to generate the fast response signal. ### Claim 4 (depends on 3) The switching regulator of claim 3, wherein the fast response signal generation circuit obtains an average of the low-pass filtered signal and the reference signal as the fast response signal. ### Claim 5 (depends on 2) The switching regulator of claim 2, wherein the controller circuit further includes a second low-pass filter, which is configured to operably generate the fast response signal by low-pass filtering the reference signal based on a second predetermined bandwidth; wherein the second predetermined bandwidth is larger than the first predetermined bandwidth. ### Claim 6 (depends on 1) The switching regulator of claim 1, wherein the clock signal has a fixed frequency or a frequency correlated to an inductor current flowing through the inductor. ### Claim 7 (depends on 1) The switching regulator of claim 1, wherein the controller circuit further includes a dynamic voltage regulation circuit, wherein the dynamic voltage regulation circuit changes the target level of the output voltage according to a request signal, so as to generate the reference signal and the low-pass filtered signal, to dynamically regulate the output voltage. ### Claim 8 (depends on 1) The switching regulator of claim 1, wherein the first amplification circuit includes: a transconductance amplifier, which is configured to operably generate a transconductance current according to a difference between the reference signal and the feedback signal, or a difference between the low-pass filtered signal and the feedback signal; and a compensation circuit, which is coupled to the transconductance amplifier, and is configured to operably generate the amplification signal according to the transconductance current which charges and discharges a capacitor in the compensation circuit. ### Claim 9 (depends on 1) The switching regulator of claim 1, wherein the adjustment signal is configured to adaptively adjust the ramp signal so as to adaptively adjust a conduction time or a duty of the pulse width modulation signal. ### Claim 10 (depends on 1) The switching regulator of claim 1, wherein when the target level changes from a relatively lower first target level to a relatively higher second target level, and the feedback signal is lower than the fast response signal, the amplification signal increases, and the second amplification circuit sinks current to decrease a slope of the ramp signal, so as to extend a conduction time of the power switch; and wherein when the feedback signal is higher than the fast response signal, the amplification signal decreases, to increase the slope of the ramp signal, so as to decrease an increase rate of the output voltage, for mitigating or avoiding an overshoot of the output voltage. ### Claim 11 (depends on 1) The switching regulator of claim 1, wherein when the target level changes from a relatively higher first target level to a relatively lower second target level, and the feedback signal is higher than the fast response signal, the amplification signal decreases, and the second amplification circuit sources current to increase a slope of the ramp signal, so as to extend a non-conduction time of the power switch; and wherein when the feedback signal is lower than the fast response signal, the amplification signal increases, to decrease the slope of the ramp signal, and the power switch is turned ON, so as to decrease a decrease rate of the output voltage, for mitigating or avoiding an undershoot of the output voltage. ### Claim 12 A controller circuit for use in a switching regulator, wherein the switching regulator includes a power stage circuit and the controller circuit, the power stage circuit including an inductor and at least one power switch, wherein the at least one power switch is coupled to the inductor, and is configured to operate according to a switch control signal, to control a conduction status of the inductor, so as to convert an input voltage to an output voltage; wherein the controller circuit is coupled to the power stage circuit, and is configured to operably generate the switch control signal according to a feedback signal and a reference signal, wherein the feedback signal related to the output voltage and the reference signal is related to a dynamic change of a target level of the output voltage, the controller circuit comprising: a first amplification circuit, which is configured to operably generate an amplification signal according to a difference between a low-pass filtered signal and the feedback signal, wherein the low-pass filtered signal is related to a signal generated by low-pass filtering the reference signal based on a first predetermined bandwidth; a second amplification circuit, which is configured to operably generate an adjustment signal according to a difference between the feedback signal and a fast response signal; a ramp signal generation circuit, which is configured to operably generate a ramp signal according to a clock signal; and a comparator, which is configured to operably compare the amplification signal and the ramp signal, to generate a pulse width modulation (PWM) signal, wherein the controller circuit generates the switch control signal according to the PWM signal; wherein the adjustment signal is configured to operably adaptively adjust the amplification signal or the ramp signal, to reduce a response time or to mitigate or avoid an overshoot or an undershoot of the output voltage; wherein a voltage level of the fast response signal is between a voltage level of the low-pass filtered signal and a voltage level of the reference signal. ### Claim 13 (depends on 12) The controller circuit of claim 12, further comprising a first low-pass filter, which is configured to operably low-pass filter the reference signal to generate the low-pass filtered signal based on the first predetermined bandwidth. ### Claim 14 (depends on 13) The controller circuit of claim 13, further comprising a quick response signal generation circuit, which is configured to operably perform a linear weighting operation on the low-pass filtered signal and the reference signal to generate the fast response signal. ### Claim 15 (depends on 14) The controller circuit of claim 14, wherein the fast response signal generation circuit obtains an average of the low-pass filtered signal and the reference signal as the fast response signal. ### Claim 16 (depends on 12) The controller circuit of claim 12, further comprising a second low-pass filter, which is configured to operably generate the fast response signal by low-pass filtering the reference signal based on a second predetermined bandwidth; wherein the second predetermined bandwidth is larger than the first predetermined bandwidth. ### Claim 17 (depends on 12) The controller circuit of claim 12, wherein the clock signal has a fixed frequency or a frequency related to an inductor current flowing through the inductor. ### Claim 18 (depends on 12) The controller circuit of claim 12, further comprising a dynamic voltage regulation circuit, wherein the dynamic voltage regulation circuit changes the target level of the output voltage according to a request signal, so as to generate the reference signal and the low-pass filtered signal, to dynamically regulate the output voltage. ### Claim 19 (depends on 12) The controller circuit of claim 12, wherein the first amplification circuit includes: a transconductance amplifier, which is configured to operably generate a transconductance current according to a difference between the reference signal and the feedback signal, or a difference between the low-pass filtered signal and the feedback signal; and a compensation circuit, which is coupled to the transconductance amplifier, and is configured to operably generate the amplification signal according to the transconductance current which charges and discharges a capacitor in the compensation circuit. ### Claim 20 (depends on 12) The controller circuit of claim 12, wherein the adjustment signal is configured to adaptively adjust the ramp signal so as to adaptively adjust a conduction time or a duty of the pulse width modulation signal. ### Claim 21 (depends on 12) The controller circuit of claim 12, wherein when the target level changes from a relatively lower first target level to a relatively higher second target level, and the feedback signal is lower than the fast response signal, the amplification signal increases, and the second amplification circuit sinks current to decrease a slope of the ramp signal, so as to extend a conduction time of the power switch; and wherein when the feedback signal is higher than the fast response signal, the amplification signal decreases, to increase the slope of the ramp signal, so as to decrease an increase rate of the output voltage, for mitigating or avoiding an overshoot of the output voltage. ### Claim 22 (depends on 12) The controller circuit of claim 12, wherein when the target level changes from a relatively higher first target level to a relatively lower second target level, and the feedback signal is higher than the fast response signal, the amplification signal decreases, and the second amplification circuit sources current to increase a slope of the ramp signal, so as to extend a non-conduction time of the power switch; and wherein when the feedback signal is lower than the fast response signal, the amplification signal increases, to decrease the slope of the ramp signal, and the power switch is turned ON, so as to decrease a decrease rate of the output voltage, for mitigating or avoiding an undershoot of the output voltage. ### Claim 23 A control method for controlling a switching regulator, comprising: operating a power switch according to a switch control signal, to control a conduction status of an inductor, so as to convert an input voltage to an output voltage; generating an amplification signal according to a difference between a low-pass filtered signal and a feedback signal, wherein the feedback signal is related to the output voltage and wherein the low-pass filtered signal is related to a signal generated by low-pass filtering the reference signal based on a first predetermined bandwidth, and wherein the reference signal is related to dynamic change of a target level of the output voltage; generating an adjustment signal according to a difference between the feedback signal and a fast response signal; generating a ramp signal according to a clock signal; and comparing the amplification signal and the ramp signal, to generate a pulse width modulation (PWM) signal, so as to generate the switch control signal according to the PWM signal; wherein the adjustment signal is configured to operably adaptively adjust the amplification signal or the ramp signal, to reduce a response time or to mitigate or avoid an overshoot or an undershoot of the output voltage; wherein a voltage level of the fast response signal is between a voltage level of the low-pass filtered signal and a voltage level of the reference signal. ### Claim 24 (depends on 23) The control method of claim 23, further comprising: performing a linear weighting operation on the low-pass filtered signal and the reference signal to generate the fast response signal. ### Claim 25 (depends on 24) The control method of claim 24, wherein the fast response signal is an average of the low-pass filtered signal and the reference signal. ### Claim 26 (depends on 23) The control method of claim 23, further comprising generating the fast response signal by low-pass filtering the reference signal based on a second predetermined bandwidth; wherein the second predetermined bandwidth is larger than the first predetermined bandwidth. ### Claim 27 (depends on 23) The control method of claim 23, wherein the clock signal has a fixed frequency or a frequency correlated to an inductor current flowing through the inductor. ### Claim 28 (depends on 23) The control method of claim 23, further comprising: changing the target level of the output voltage according to a request signal, so as to generate the reference signal and the low-pass filtered signal, to dynamically regulate the output voltage. ### Claim 29 (depends on 23) The control method of claim 23, wherein the adjustment signal is configured to adaptively adjust the ramp signal to adaptively adjust a conduction time or a duty of the pulse width modulation signal. ### Claim 30 (depends on 23) The control method of claim 23, wherein when the target level changes from a relatively lower first target level to a relatively higher second target level, and the feedback signal is lower than the fast response signal, the amplification signal increases, to decreases a slope of the ramp signal, so as to extend a conduction time of the power switch; and wherein when the feedback signal is higher than the fast response signal, the amplification signal decreases, to increase the slope of the ramp signal, so as to decrease an increase rate of the output voltage, for mitigating or avoiding an overshoot of the output voltage. ### Claim 31 (depends on 23) The control method of claim 23, wherein when the target level changes from a relatively higher first target level to a relatively lower second target level, and the feedback signal is higher than the fast response signal, the amplification signal decreases, to increase a slope of the ramp signal, so as to extend a non-conduction time of the power switch; and wherein when the feedback signal is lower than the fast response signal, the amplification signal increases, to decrease the slope of the ramp signal, and the power switch is turned ON, so as to decrease a decrease rate of the output voltage, for mitigating or avoiding an undershoot of the output voltage.