# US 11,909,312 B2 · Regulated voltage systems and methods using intrinsically varied process characteristics > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,909,312 B2 - Document ID: US11909312B2 - Status: Granted - Kind: B2 - Application number: 18/113,501 - Filed: 2023-02-23 - Published: 2023-07-06 - Granted: 2024-02-20 - Earliest claimed: 2016-07-25 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Co., Inc. - Inventors: Chia Liang Tai - Web page: https://patentgrep.com/patent/US11909312B2 ## CPC - H02M 3/07: using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} - G01R 19/16576: {comparing DC or AC voltage with one threshold (G01R19/16514, G01R19/16519, G01R19/16528, G01R19/16533 and G01R19/1659 take precedence)} - H02M 3/072: {adapted to generate an output voltage whose value is lower than the input voltage} - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) ## Abstract A regulator system includes a multi-bit detector system and a multi-cell charge/discharge circuit. The multi-bit detector system includes a plurality of detectors. Each of the plurality of detectors has a predetermined threshold voltage. The multi-cell charge/discharge circuit includes a plurality of charge pumps. Each of the charge pumps is configured to generate a predetermined charge. Each of the charge pumps is associated with a predetermined threshold voltage of the detector circuit. ## Claims ### Claim 1 A detector circuit, comprising: a comparator configured to generate an output based on a comparison of a reference voltage to a trigger voltage; and a compensation circuit comprising at least one compensation transistor configured to compensate for at least one process variation of the comparator, wherein the comparator comprises: a positive reference system including a PMOS current source and a PMOS pass-gate; a negative reference system including an NMOS current source and an NMOS pass-gate; and a transistor coupled between a pump output voltage input and at least one of the PMOS pass-gate and the NMOS pass-gate. ### Claim 2 (depends on 1) The detector circuit of claim 1, wherein the compensation circuit includes at least one compensation transistor configured to compensate for variations in a constant transconductance bias current of the comparator. ### Claim 3 (depends on 2) The detector circuit of claim 2, wherein the at least one compensation transistor comprises an NMOS transistor having a gate coupled to an output of a current source of the comparator, a source coupled to a pass-gate transistor of the comparator, and a drain coupled to ground. ### Claim 4 (depends on 1) The detector circuit of claim 1, wherein the compensation circuit includes at least one compensation transistor configured to compensate for process variations in one or more of a width, a length, or a threshold voltage of at least one transistor of the comparator, and wherein the at least one compensation transistor comprises a PMOS transistor having a gate coupled to an output of a two-NMOS transistor comparison circuit, a source coupled to pass-gate transistor of the comparator, and a drain coupled to ground. ### Claim 5 (depends on 1) The detector circuit of claim 1, wherein the positive reference system is configured to generate an output signal for at least one charge pump during a positive phase of a load current, and wherein the negative reference system is configured to generate the output signal for the at least one charge pump during a negative phase of the load current. ### Claim 6 (depends on 5) The detector circuit of claim 5, wherein the detector circuit is configured to generate an n-bit output to activate one or more of the at least one charge pump based on a comparison between a reference voltage and an output voltage of a multi-cell charge/discharge circuit. ### Claim 7 A regulator system, comprising: a plurality of detectors each comprising: a current comparator configured to generate an output by comparing a reference voltage to a trigger voltage, wherein the trigger voltage is determined by one or more process variations of the current comparator; and a compensation circuit comprising at least one compensation transistor configured to compensate for at least one process variations of the current comparator; and a plurality of charge pumps each associated with at least one of the plurality of detectors, wherein each of the charge pumps is configured to generate a predetermined charge, wherein the current comparator comprises: a positive reference system including a PMOS current source and a PMOS pass-gate; a negative reference system including an NMOS current source and an NMOS pass-gate; and a transistor coupled between a pump output voltage input and at least one of the PMOS pass-gate and the NMOS pass-gate. ### Claim 8 (depends on 7) The regulator system of claim 7, wherein the predetermined charge generated by each of the charge pumps is equal. ### Claim 9 (depends on 7) The regulator system of claim 7, wherein the at least one compensation transistor is further configured to compensate for variations in a constant transconductance bias current of the comparator. ### Claim 10 (depends on 9) The regulator system of claim 9, wherein the at least one compensation transistor comprises an NMOS transistor having a gate coupled to an output of a current source of the current comparator, a source coupled to a pass-gate transistor of the current comparator, and a drain coupled to ground. ### Claim 11 (depends on 7) The regulator system of claim 7, wherein each of the plurality of detectors is configured to generate an n-bit output to activate a respective one of the plurality of charge pumps based on a comparison between a reference voltage and an output voltage of a multi-cell charge/discharge circuit. ### Claim 12 (depends on 7) The regulator system of claim 7, wherein the compensation circuit includes at least one compensation transistor configured to compensate for process variations in one or more of a width, a length, or a threshold voltage of at least one transistor of the current comparator, and wherein the at least one compensation transistor comprises a PMOS transistor having a gate coupled to an output of a two-NMOS transistor comparison circuit, a source coupled to pass-gate transistor of the current comparator, and a drain coupled to ground. ### Claim 13 A detector circuit, comprising: a comparator configured to generate an output based on a comparison of a reference voltage to a trigger voltage; a compensation circuit comprising at least one compensation transistor configured to compensate for at least one process variation of the comparator; and a plurality of charge pumps each configured to generate a pre-charge voltage and a boost voltage, wherein each of the plurality of charge pumps is configured to output the pre-charge voltage in response to a first signal and the boost voltage in response to a second signal, wherein the comparator comprises: a positive reference system including a PMOS current source and a PMOS pass-gate; a negative reference system including an NMOS current source and an NMOS pass-gate; and a transistor coupled between a pump output voltage input and at least one of the PMOS pass-gate and the NMOS pass-gate. ### Claim 14 (depends on 13) The detector circuit of claim 13, wherein the compensation circuit includes at least one compensation transistor configured to compensate for variations in the reference voltage. ### Claim 15 (depends on 14) The detector circuit of claim 14, wherein the at least one compensation transistor comprises an NMOS transistor having a gate coupled to an output of a current source of the current comparator, a source coupled to a pass-gate transistor of the current comparator, and a drain coupled to ground. ### Claim 16 (depends on 13) The detector circuit of claim 13, wherein the detector circuit is configured to generate an n-bit output to activate one or more of the plurality of charge pumps based on an output of the comparator, wherein n is an integer greater than 1. ### Claim 17 (depends on 13) The detector circuit of claim 13, wherein the predetermined charge generated by each of the charge pumps is equal. ### Claim 18 (depends on 13) The detector circuit of claim 13, wherein each of the plurality of pumping cells are shunted together. ### Claim 19 (depends on 13) The detector circuit of claim 13, wherein each of the charge pumps is configured to generate an identical charge. ### Claim 20 (depends on 13) The detector circuit of claim 13, wherein the detector circuit is configured to generate an n-bit output to activate one or more of the charge pumps based on a comparison between a reference voltage and an output voltage of the multi-cell charge/discharge circuit.