# US 11,908,953 B2 · Manufacturing method of memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,908,953 B2 - Document ID: US11908953B2 - Status: Granted - Kind: B2 - Application number: 18/081,703 - Filed: 2022-12-15 - Published: 2023-04-20 - Granted: 2024-02-20 - Earliest claimed: 2019-08-30 - Assignees: Winbond Electronics Corp. - Applicants: Winbond Electronics Corp. - Inventors: Che-Jui Hsu; Ying-Fu Tung; Chun-Sheng Lu; Kuo-Feng Huang; Yu-Chi Kuo; Wang-Ta Li - Web page: https://patentgrep.com/patent/US11908953B2 ## CPC - H10D 30/68: Floating-gate IGFETs - H10B 41/30: characterised by the memory core region - H10B 41/35: with a cell select transistor, e.g. NAND - H10D 30/0411: {of FETs having floating gates} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A manufacturing method of a memory device are provided. The method includes following steps. A gate stacking structure is formed over a substrate. A first insulating layer, a second insulating layer and a mask material layer are sequentially formed over the substrate to cover the gate stacking structure. An ion implantation process is performed on the mask material layer to form a doped portion in the mask material layer. The doped portion caps on a top portion of the gate stacking structure. A first patterning process is performed on the mask material layer using the doped portion as a shadow mask to remove a bottom portion of the mask material layer extending along a surface of the substrate. A second patterning process is performed to remove the doped portion of the mask material layer and an exposed bottom portion of the second insulating layer surrounding the gate stacking structure. ## Claims ### Claim 1 A manufacturing method of a memory device, comprising: forming a gate stacking structure over a substrate; sequentially forming a first insulating layer, a second insulating layer and a mask material layer over the substrate to cover the gate stacking structure; performing an ion implantation process on the mask material layer, to form a doped portion in the mask material layer, wherein the doped portion caps on a top portion of the gate stacking structure; performing a first patterning process on the mask material layer by using the doped portion as a shadow mask, to remove a bottom portion of the mask material layer extending along a surface of the substrate; and performing a second patterning process to remove the doped portion of the mask material layer and an exposed bottom portion of the second insulating layer surrounding the gate stacking structure, wherein a remained portion of the mask material layer forms a first spacer. ### Claim 2 (depends on 1) The manufacturing method of the memory device according to claim 1, further comprising performing a decoupled plasma nitridation treatment on the doped portion of the mask material layer after performing the ion implantation process on the mask material layer. ### Claim 3 (depends on 1) The manufacturing method of the memory device according to claim 1, wherein the doped portion has a first etching selectivity with respect to the second insulating layer, and has a second etching selectivity with respect to an undoped portion of the mask material layer, the first etching selectivity is less than the second etching selectivity. ### Claim 4 (depends on 1) The manufacturing method of the memory device according to claim 1, wherein the ion implantation process comprises a first oblique ion implantation process and a second oblique ion implantation process, and ions strike the mask material layer from opposite sides of the gate stacking structure during the first oblique ion implantation process and the second oblique ion implantation process. ### Claim 5 (depends on 1) The manufacturing method of the memory device according to claim 1, wherein the second patterning process includes alternately performing an etching process and a deposition process. ### Claim 6 (depends on 1) The manufacturing method of the memory device according to claim 1, further comprising: forming a third insulating layer on the substrate to cover the first spacer and the second insulating layer; and removing a horizontal portion of the third insulating layer extending over the gate stacking structure and along a surface of the substrate, wherein a remained portion of the third insulating layer forms a second spacer. ### Claim 7 (depends on 1) The manufacturing method of the memory device according to claim 1, further comprising forming an insulating plug over a topmost surface of the second insulating layer. ### Claim 8 (depends on 1) The manufacturing method of the memory device according to claim 1, wherein a material of the first insulating layer comprises silicon oxide. ### Claim 9 (depends on 1) The manufacturing method of the memory device according to claim 1, wherein a material of the second insulating layer comprises silicon nitride. ### Claim 10 (depends on 1) The manufacturing method of the memory device according to claim 1, wherein after the first spacer is formed, the second insulating layer has an extending portion extending outwardly from the sidewall of the gate stacking structure along the surface of the substrate, and a terminal surface of the extending portion is substantially coplanar with a surface of the first spacer. ### Claim 11 (depends on 10) The manufacturing method of the memory device according to claim 10, wherein the first insulating layer has an extending portion extending outwardly from the sidewall of the gate stacking structure along the surface of the substrate, and a lateral spacing from the gate stacking structure to a terminal surface of the extending portion of the first insulating layer is greater than a lateral spacing from the gate stacking structure to the terminal surface of the extending portion of the second insulating layer. ### Claim 12 (depends on 1) The manufacturing method of the memory device according to claim 1, wherein after the first spacer is formed, a portion of the second insulating layer covering a top corner region of the gate stacking structure has an inclined surface, and an extending direction of the inclined surface of the second insulating layer is intersected with a surface of the substrate and a normal direction of the substrate. ### Claim 13 (depends on 1) The manufacturing method of the memory device according to claim 1, wherein after the first spacer is formed, a portion of the second insulating layer covering a top corner region of the gate stacking structure has a curved surface. ### Claim 14 (depends on 1) The manufacturing method of the memory device according to claim 1, wherein after the first spacer is formed, the second insulating layer covers a surface of the first insulating layer on a top surface and a sidewall of the gate stacking structure.