# US 11,908,952 B2 · Semiconductor devices and manufacturing methods thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,908,952 B2 - Document ID: US11908952B2 - Status: Granted - Kind: B2 - Application number: 17/840,737 - Filed: 2022-06-15 - Published: 2022-09-29 - Granted: 2024-02-20 - Earliest claimed: 2017-08-29 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Jung Gil Yang; Woo Seok Park; Dong Chan Suh; Seung Min Song; Geum Jong Bae; Dong Il Bae - Web page: https://patentgrep.com/patent/US11908952B2 ## CPC - H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)} - B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic - H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors} - H10D 30/0193: {by modifying properties of the stacked channels} - H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels - H10D 30/506: {having different thicknesses, sizes or shapes} - H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes} - H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around} - H10D 62/121: {oriented parallel to substrates} - H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)} - H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)} - H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe - H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes} - H10D 30/503: {having non-rectangular cross-sections} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES ## Abstract A semiconductor device includes a substrate, a plurality of channel layers stacked on the substrate, a gate electrode surrounding the plurality of channel layers, and embedded source/drain layers on opposing sides of the gate electrode. The embedded source/drain layers each have a first region and a second region on the first region. The second region has a plurality of layers having different compositions. ## Claims ### Claim 1 A semiconductor device, comprising: a substrate; a channel on the substrate; a gate electrode extending on the channel; and source/drain structures in recess regions on opposing sides of the gate electrode, the source/drain structures each comprising a first epitaxial layer and a second epitaxial layer on the first epitaxial layer, wherein the second epitaxial layer is in a center region of each of the source/drain structures, wherein the first epitaxial layer surrounds a bottom surface and both side surfaces of the second epitaxial layer, wherein the side surfaces of the second epitaxial layer each comprise first portions that are inclined so that a width of the second epitaxial layer decreases toward the substrate, wherein the second epitaxial layer fills more than half of each of the recess regions and comprises a recess portion in an upper surface thereof, and wherein the second epitaxial layer has a first length in a first direction perpendicular to an upper surface of the substrate and has a second length, smaller than the first length, in a second direction perpendicular to the first direction. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the side surfaces of the second epitaxial layer further comprise: second portions that are curved downwardly from upper portions of the first epitaxial layer and are connected to upper ends of the first portions; and third portions that are curved from lower ends of the first portions. ### Claim 3 (depends on 2) The semiconductor device of claim 2, wherein a first width of the second epitaxial layer between the second portions is greater than a second width of a portion of the first epitaxial layer contacting the first portions of the second epitaxial layer on each of the side surfaces of the second epitaxial layer. ### Claim 4 (depends on 2) The semiconductor device of claim 2, wherein the second portions of the side surfaces of the second epitaxial layer and an upper surface of the second epitaxial layer are connected to form an angled shape toward outer surfaces of each the source/drain structures. ### Claim 5 (depends on 2) The semiconductor device of claim 2, wherein a surface of the first epitaxial layer contacting the second portions of the side surfaces of the second epitaxial layer comprises a curved portion. ### Claim 6 (depends on 1) The semiconductor device of claim 1, wherein the second epitaxial layer covers a portion of an upper surface of the first epitaxial layer. ### Claim 7 (depends on 1) The semiconductor device of claim 1, wherein the first epitaxial layer and the second epitaxial layer each comprise silicon germanium, and wherein a germanium content of the second epitaxial layer is greater than a germanium content of the first epitaxial layer. ### Claim 8 (depends on 1) The semiconductor device of claim 1, wherein the source/drain structures further comprise a third epitaxial layer on the second epitaxial layer, and wherein the first epitaxial layer includes 17 at % to 27 at % Ge, the second epitaxial layer includes 37 at % to 47 at % Ge, and the third epitaxial layer includes 50 at % to 60 at % Ge. ### Claim 9 A semiconductor device, comprising: a substrate; a channel on the substrate; a gate electrode on the channel, the gate electrode extending in a first direction; source/drain structures on opposing sides of the gate electrode, the source/drain structures each comprising a first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and a third epitaxial layer on the second epitaxial layer; and spacers on side surfaces of the gate electrode, the spacers being in contact with the third epitaxial layer, wherein the first epitaxial layer surrounds a bottom surface and side surfaces of the second epitaxial layer, wherein the side surfaces of the second epitaxial layer comprise first portions that are inclined so that a width of the second epitaxial layer decreases toward the substrate, second portions that are curved downwardly from upper portions of the first epitaxial layer and are connected to upper ends of the first portions, third portions curved from lower ends of the first portions, wherein a first width of the second epitaxial layer between the second portions is greater than a second width of a portion of the first epitaxial layer contacting the first portions of the second epitaxial layer on each of the side surfaces of the second epitaxial layer, wherein at least one of the source/drain structures comprises an upper portion having a convex shape protruding upwardly to a level higher than an upper surface of the channel, wherein the at least one of the source/drain structures comprises a middle portion below the upper portion, wherein a width of the upper portion in a second direction perpendicular to the first direction is smaller than a width of the middle portion in the second direction, wherein the third epitaxial layer comprises a convex upper surface. ### Claim 10 (depends on 9) The semiconductor device of claim 9, wherein the first epitaxial layer includes 17 at % to 27 at % Ge, the second epitaxial layer includes 37 at % to 47 at % Ge, and the third epitaxial layer includes 50 at % to 60 at % Ge. ### Claim 11 (depends on 9) The semiconductor device of claim 9, wherein the second portions of the side surfaces of the second epitaxial layer and an upper surface of the second epitaxial layer are connected to form an angled shape toward outer surfaces of each the source/drain structures. ### Claim 12 A semiconductor device, comprising: a substrate; a channel on the substrate; a gate electrode on the channel; and source/drain structures on opposing sides of the gate electrode, the source/drain structures each comprising a first epitaxial layer and a second epitaxial layer having different compositions from each other, wherein the second epitaxial layer is in a center region of each of the source/drain structures, wherein the first epitaxial layer surrounds a bottom surface and both side surfaces of the second epitaxial layer, wherein the side surfaces of the second epitaxial layer each comprise first portions that are inclined so that a width of the second epitaxial layer decreases toward the substrate and second portions that are curved downwardly from upper portions of the first epitaxial layer and are connected to upper ends of the first portions, and wherein the first epitaxial layer comprises outer side surfaces having substantially vertical portions. ### Claim 13 (depends on 12) The semiconductor device of claim 12, wherein a first width of the second epitaxial layer between the second portions is greater than a second width of a portion of the first epitaxial layer contacting the first portions of the second epitaxial layer on each of the side surfaces of the second epitaxial layer. ### Claim 14 (depends on 12) The semiconductor device of claim 12, wherein the second portions of the side surfaces of the second epitaxial layer and an upper surface of the second epitaxial layer are connected to form an angled shape toward outer surfaces of each the source/drain structures. ### Claim 15 (depends on 12) The semiconductor device of claim 12, wherein a surface of the first epitaxial layer contacting the second portions of the side surfaces of the second epitaxial layer comprises a curved portion. ### Claim 16 (depends on 12) The semiconductor device of claim 12, wherein an upper surface of the second epitaxial layer comprises a recessed portion. ### Claim 17 (depends on 12) The semiconductor device of claim 12, wherein the source/drain structures further comprise a third epitaxial layer on the second epitaxial layer, and wherein the first epitaxial layer includes 17 at % to 27 at % Ge, the second epitaxial layer includes 37 at % to 47 at % Ge, and the third epitaxial layer includes 50 at % to 60 at % Ge. ### Claim 18 (depends on 12) The semiconductor device of claim 12, wherein the second epitaxial layer fills more than half of each of recess regions in which the source/drain structures are located, and wherein the second epitaxial layer has a first length in a first direction perpendicular to an upper surface of the substrate and has a second length, smaller than the first length, in a second direction perpendicular to the first direction.