# US 11,908,949 B2 · Semiconductor device and manufacturing method thereof

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 11,908,949 B2
- Document ID: US11908949B2
- Status: Granted
- Kind: B2
- Application number: 18/077,452
- Filed: 2022-12-08
- Published: 2023-04-06
- Granted: 2024-02-20
- Earliest claimed: 2018-02-28
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Yuki Hata; Katsuaki Tochibayashi; Junpei Sugao; Shunpei Yamazaki
- Web page: https://patentgrep.com/patent/US11908949B2

## CPC

- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10B 12/05: {Making the transistor}
- H10B 12/312: {with a bit line higher than the capacitor}
- H10B 12/36: {the transistor being a FinFET}
- H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs}
- H10P 30/40: into insulating materials
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device with a high on-state current is provided. The semiconductor device includes a first oxide, a second oxide over the first oxide, a third oxide over the second oxide, a first insulator over the third oxide, a conductor over the first insulator, a second insulator in contact with the second oxide and the third oxide, and a third insulator over the second insulator; the second oxide includes first region to fifth regions; the resistance of the first region and the resistance of the second region are lower than the resistance of the third region; the resistance of the fourth region and the resistance of the fifth region are lower than the resistance of the third region and higher than the resistance of the first region and the resistance of the second region; and the conductor is provided over the third region, the fourth region, and the fifth region to overlap with the third region, the fourth region, and the fifth region.

## Claims

### Claim 1

A method for manufacturing a semiconductor device, comprising:
forming a first oxide and a second oxide over the first oxide;
forming a first insulating film covering the first oxide and the second oxide;
forming a first dummy gate over the first insulating film to overlap with the second oxide;
adding a first dopant to the second oxide using the first dummy gate as a mask;
forming a second dummy gate by removing part of the first dummy gate;
exposing part of the second oxide from the second dummy gate;
adding a second dopant to the second oxide using the second dummy gate as a mask;
forming a second insulating film covering the first insulating film and the second dummy gate;
forming a third insulating film over the second insulating film;
removing part of the second insulating film and part of the third insulating film until a top portion of the second dummy gate is exposed;
forming an opening by removing the second dummy gate, part of the second insulating film, and part of the first insulating film;
forming a third oxide, a fourth insulating film, and a conductive film in this order to be embedded in the opening; and
removing part of the third oxide, part of the fourth insulating film, and part of the conductive film until a top portion of the third insulating film is exposed.

### Claim 2 (depends on 1)

The method for manufacturing the semiconductor device, according to claim 1,
wherein phosphorus or boron is used for the first dopant and the second dopant.

### Claim 3 (depends on 1)

The method for manufacturing the semiconductor device according to claim 1,
wherein the first dopant is added more than the second dopant.

### Claim 4 (depends on 1)

The method for manufacturing the semiconductor device, according to claim 1,
wherein the first dopant and the second dopant are added by an ion implantation method or an ion doping method.

### Claim 5 (depends on 1)

The method for manufacturing the semiconductor device, according to claim 1,
wherein the first dummy gate contains carbon.

### Claim 6 (depends on 1)

The method for manufacturing the semiconductor device, according to claim 1,
wherein the second dummy gate is formed by ashing treatment using an oxygen radical.