# US 11,908,947 B2 · Semiconductor device

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- Number: US 11,908,947 B2
- Document ID: US11908947B2
- Status: Granted
- Kind: B2
- Application number: 17/628,091
- Filed: 2020-07-27
- Published: 2022-08-18
- Granted: 2024-02-20
- Earliest claimed: 2019-08-08
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Munehiro Kozuma; Takahiko Ishizu; Takeshi Aoki; Masashi Fujita; Kazuma Furutani; Kousuke Sasaki
- Web page: https://patentgrep.com/patent/US11908947B2

## CPC

- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- G06F 7/5443: {Sum of products (for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00)}
- G06F 12/00: Accessing, addressing or allocating within memory systems or architectures (digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06)
- G11C 7/1069: {I/O lines read out arrangements}
- G11C 7/1096: {Write circuits, e.g. I/O line write drivers}
- G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
- G11C 7/14: Dummy cell management; Sense reference voltage generators
- G11C 11/404: with one charge-transfer gate, e.g. MOS transistor, per cell
- G11C 11/405: with three charge-transfer gates, e.g. MOS transistors, per cell
- G11C 11/409: Read-write [R-W] circuits
- G11C 11/54: using elements simulating biological cells, e.g. neuron
- G11C 14/00: Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
- G11C 16/10: Programming or data input circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- H03K 3/037: Bistable circuits
- H03K 3/356: Bistable circuits
- H10B 12/00: Dynamic random access memory [DRAM] devices
- H10B 12/50: {Peripheral circuit region structures}
- H10D 84/00: Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D 84/01: Manufacture or treatment
- H10D 84/0126: {the components including insulated gates, e.g. IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 86/01: Manufacture or treatment
- H10D 86/021: {of multiple TFTs}
- H10D 87/00: Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
- G11C 11/005: {comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells}
- G11C 2211/5641: Multilevel memory having cells with different number of storage levels
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/60: wherein the TFTs are in active matrices
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor device having a novel structure is provided. The semiconductor device includes a CPU and an accelerator. The accelerator includes a first memory circuit and an arithmetic circuit. The first memory circuit includes a first transistor. The first transistor includes a semiconductor layer containing a metal oxide in a channel formation region. The arithmetic circuit includes a second transistor. The second transistor includes a semiconductor layer containing silicon in a channel formation region. The first transistor and the second transistor are provided to be stacked. The CPU includes a CPU core including a flip-flop provided with a backup circuit. The backup circuit includes a third transistor. The third transistor includes a semiconductor layer containing a metal oxide in a channel formation region.

## Claims

### Claim 1

A semiconductor device comprising:
a CPU; and
an accelerator,
wherein the accelerator comprises a first memory circuit, a driver circuit, and an arithmetic circuit,
wherein the first memory circuit comprises a first transistor,
wherein the first transistor comprises a semiconductor layer comprising a metal oxide in a channel formation region,
wherein the driver circuit comprises a writing circuit and a reading circuit,
wherein the writing circuit is configured to switch data to be written to the first memory circuit to a binary or ternary voltage value in accordance with a switching signal, a writing control signal, and a data signal and outputting the voltage value,
wherein the reading circuit is configured to switch the voltage value to binary or ternary data corresponding to the voltage level retained in the first memory circuit in accordance with a first reference voltage and a second reference voltage and reading out the data,
wherein the driver circuit and the arithmetic circuit each comprise a second transistor,
wherein the second transistor comprises a semiconductor layer comprising silicon in a channel formation region, and
wherein the first transistor is stacked over the second transistor.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1,
wherein the arithmetic circuit performs a product-sum operation.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1,
wherein the metal oxide comprises In, Ga, and Zn.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1,
wherein the first transistor is electrically connected to a read bit line, and
wherein the read bit line is electrically connected to the arithmetic circuit through a wiring substantially perpendicular to a substrate with the second transistor.

### Claim 5

A semiconductor device comprising:
a CPU; and
an accelerator,
wherein the accelerator comprises a first memory circuit and an arithmetic circuit,
wherein the first memory circuit comprises a first transistor,
wherein the first transistor comprises a semiconductor layer comprising a metal oxide in a channel formation region,
wherein the arithmetic circuit comprises a second transistor,
wherein the second transistor comprises a semiconductor layer comprising silicon in a channel formation region,
wherein the CPU comprises a CPU core comprising a flip-flop with a backup circuit,
wherein the backup circuit comprises a third transistor,
wherein the third transistor comprises a semiconductor layer comprising a metal oxide in a channel formation region, and
wherein the first transistor is stacked over the second transistor.

### Claim 6 (depends on 5)

The semiconductor device according to claim 5,
wherein the backup circuit is configured to retain data retained in the flip-flop in a state where supply of a power supply voltage is stopped when the CPU does not operate.

### Claim 7 (depends on 5)

The semiconductor device according to claim 5,
wherein the arithmetic circuit performs a product-sum operation.

### Claim 8 (depends on 5)

The semiconductor device according to claim 5,
wherein the first transistor is electrically connected to a read bit line, and
wherein the read bit line is electrically connected to the arithmetic circuit through a wiring substantially perpendicular to a substrate with the second transistor.

### Claim 9

A semiconductor device comprising:
a CPU; and
an accelerator,
wherein the accelerator comprises a first memory circuit, a driver circuit, and an arithmetic circuit,
wherein the first memory circuit comprises a first transistor,
wherein the first transistor comprises a semiconductor layer comprising a metal oxide in a channel formation region,
wherein the driver circuit comprises a writing circuit and a reading circuit,
wherein the writing circuit is configured to switch data to be written to the first memory circuit to a binary or ternary voltage value in accordance with a switching signal, a writing control signal, and a data signal and outputting the voltage value,
wherein the reading circuit is configured to switch the voltage value to binary or ternary data corresponding to the voltage level retained in the first memory circuit in accordance with a first reference voltage and a second reference voltage and reading out the data,
wherein the arithmetic circuit comprises a second transistor,
wherein the second transistor comprises a semiconductor layer comprising silicon in a channel formation region,
wherein the CPU comprises a CPU core comprising a flip-flop with a backup circuit,
wherein the backup circuit comprises a third transistor,
wherein the third transistor comprises a semiconductor layer comprising a metal oxide in a channel formation region, and
wherein the first transistor is stacked over the second transistor.

### Claim 10 (depends on 9)

The semiconductor device according to claim 9,
wherein the backup circuit is configured to retain data retained in the flip-flop in a state where supply of a power supply voltage is stopped when the CPU does not operate.

### Claim 11 (depends on 9)

The semiconductor device according to claim 9,
wherein the arithmetic circuit performs a product-sum operation.

### Claim 12 (depends on 9)

The semiconductor device according to claim 9,
wherein the first transistor is electrically connected to a read bit line, and
wherein the read bit line is electrically connected to the arithmetic circuit through a wiring substantially perpendicular to a substrate with the second transistor.

### Claim 13 (depends on 1)

The semiconductor device according to claim 1,
wherein the CPU and the accelerator are electrically connected to each other through a bus.

### Claim 14 (depends on 5)

The semiconductor device according to claim 5,
wherein the CPU and the accelerator are electrically connected to each other through a bus.

### Claim 15 (depends on 9)

The semiconductor device according to claim 9,
wherein the CPU and the accelerator are electrically connected to each other through a bus.