# US 11,908,944 B2 · Contact formation for vertical field effect transistors

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- Number: US 11,908,944 B2
- Document ID: US11908944B2
- Status: Granted
- Kind: B2
- Application number: 17/447,904
- Filed: 2021-09-16
- Published: 2023-03-16
- Granted: 2024-02-20
- Earliest claimed: 2021-09-16
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Heng Wu; Lan Yu; Samuel Sung Shik Choi; Ruilong Xie
- Web page: https://patentgrep.com/patent/US11908944B2

## CPC

- H10D 30/6728: {Vertical TFTs}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 64/252: {for vertical or pseudo-vertical devices}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0195: {the components including vertical IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10W 20/037: {the barrier, adhesion or liner layers being on top of a main fill metal}
- H10W 20/082: {the openings being tapered via holes}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A vertical field effect transistor includes a top source/drain region in contact with a top portion of a channel fin extending perpendicularly from a semiconductor substrate, a bottom source/drain region is disposed above the semiconductor substrate and on opposite sidewalls of a bottom portion of the channel fin, a metal gate surrounding the channel fin is separated from the top source/drain region by a top spacer and from the bottom source/drain region by a bottom spacer, the metal gate and the top spacer are in contact with an adjacent first interlevel dielectric layer. A silicide layer is directly above an uppermost surface of the top source/drain region, and a nitride layer is directly above an uppermost surface of the silicide layer. A top source/drain contact, having a size that is substantially less than a length of the channel fin, extends until an uppermost surface of the nitride layer.

## Claims

### Claim 1

A semiconductor structure, comprising:
a channel fin extending perpendicularly from a semiconductor substrate;
a top source/drain region in contact with a top portion of the channel fin,
the top source/drain region including a bottom portion abutted by a first side of a top spacer and a top portion extending outwards from the top spacer,
a second side of the top spacer, opposing the first side, being in contact with a first interlevel dielectric layer;
a bottom source/drain region disposed above the semiconductor substrate and in contact with opposite sidewalls of a bottom portion of the channel fin;
a metal gate stack in contact with a central portion of the channel fin, the metal gate stack being separated from the top source/drain region by the top spacer and from the bottom source/drain region by a bottom spacer;
a silicide layer disposed above and in direct contact with opposite sidewalls of the top portion of the top source/drain region; and
a nitride layer disposed above and in direct contact with an uppermost surface of the silicide layer,
a topmost surface of the top spacer being in contact with opposing ends of the silicide layer and the nitride layer.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, further comprising:
a top source/drain contact extending through a second interlevel dielectric layer until an uppermost surface of the nitride layer;
a bottom source/drain contact extending through the first interlevel dielectric layer and the second interlevel dielectric layer until an uppermost surface of the bottom source/drain region; and
a gate contact extending through the first interlevel dielectric layer and the second interlevel dielectric layer until an uppermost surface of the metal gate stack.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, wherein the top portion of the top source/drain region extending outwards from the top spacer comprises a diamond-shaped epitaxial region above which the silicide layer is formed, the top spacer abutting the bottom portion of the top source/drain region including two vertical sections with respect to the semiconductor substrate disposed on opposite sides of the bottom portion of the top source/drain region and a horizontal section with respect to the semiconductor substrate disposed on opposite sides of the channel fin.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, wherein the silicide layer comprises a titanium silicide layer formed from a titanium liner during a silicide anneal process.

### Claim 5 (depends on 4)

The semiconductor structure of claim 4, wherein the nitride layer comprises a titanium nitride layer formed from the titanium liner during a nitridation process.

### Claim 6 (depends on 1)

The semiconductor structure of claim 1, wherein the top source/drain region is p-type doped for providing a P-FET device.

### Claim 7 (depends on 6)

The semiconductor structure of claim 6, further comprising:
a masking layer disposed above the first interlevel dielectric layer and above a first portion of the nitride layer not covered by the top source/drain contact, a second portion of the nitride layer being in contact with the top source/drain contact, the masking layer being in contact, on a side opposing the nitride layer, with the second interlevel dielectric layer.

### Claim 8 (depends on 1)

The semiconductor structure of claim 1, wherein the top source/drain region is n-type doped for providing a N-FET device.