# US 11,908,942 B2 · Transistors having nanostructures

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- Number: US 11,908,942 B2
- Document ID: US11908942B2
- Status: Granted
- Kind: B2
- Application number: 17/860,022
- Filed: 2022-07-07
- Published: 2022-11-03
- Granted: 2024-02-20
- Earliest claimed: 2020-04-21
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Cheng-Ting Chung; Ching-Wei Tsai; Kuan-Lun Cheng
- Web page: https://patentgrep.com/patent/US11908942B2

## CPC

- H10D 30/0193: {by modifying properties of the stacked channels}
- H10D 30/0245: {by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins}
- H10D 30/502: {characterised by the stacked channels}
- H10D 30/503: {having non-rectangular cross-sections}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/8312: {the IGFETs characterised by having different source or drain region structures, e.g. IGFETs having symmetrical source or drain regions integrated with IGFETs having asymmetrical source or drain regions}
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 62/405: {Orientations of crystalline planes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device according to the present disclosure includes a first transistor and a second transistor. The first transistor includes a plurality of first channel members and a first gate structure wrapping around each of the plurality of first channel members. The second transistor includes a plurality of second channel members and a second gate structure disposed over the plurality of second channel members. Each of the plurality of first channel members has a first width and a first height smaller than the first width. Each of the plurality of second channel members has a second width and a second height greater than the second width.

## Claims

### Claim 1

A semiconductor device, comprising:
a first transistor comprising:
first nanostructures disposed one over another and extending between a first source/drain feature and a second source/drain feature along a first direction, and
a first gate structure wrapping around each of the first nanostructures; and
a second transistor comprising:
second nanostructures disposed one over another and extending between a third source/drain feature and a fourth source/drain feature along the first direction, and
a second gate structure disposed over the second nanostructures,
wherein the first source/drain feature comprises a first width along a second direction perpendicular to the first direction,
wherein the third source/drain feature comprises a second width along the second direction,
wherein the first width is greater than the second width,
wherein the second gate structure comprises a gate dielectric layer and the gate dielectric layer disposed over two adjacent ones of the second nanostructures merge.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising:
a first source/drain contact disposed over and in electrical communication with the first source/drain feature; and
a second source/drain contact disposed over and in electrical communication with the third source/drain feature,
wherein a third width of the first source/drain contact along the second direction is greater than a fourth width of the second source/drain contact along the second direction.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein a ratio of the third width to the fourth width is between about 2 and about 10.

### Claim 4 (depends on 1)

The semiconductor device of claim 1,
wherein the first nanostructures are disposed at a first pitch,
wherein the second nanostructures are disposed at a second pitch,
wherein the first pitch is identical to the second pitch.

### Claim 5 (depends on 1)

The semiconductor device of claim 1,
wherein the first nanostructures comprise a first channel width
wherein the second nanostructures comprises a second channel width smaller than the first channel width.

### Claim 6 (depends on 5)

The semiconductor device of claim 5,
wherein the first channel width is between about 10 nm and about 60 nm,
wherein the second channel width is between about 3 nm and about 7 nm.

### Claim 7 (depends on 1)

The semiconductor device of claim 1,
wherein each of the first nanostructures comprises a first height,
wherein each of the second nanostructures comprises a second height,
wherein the second height is greater than the first height.

### Claim 8 (depends on 7)

The semiconductor device of claim 7,
wherein the first height is between about 3 nm and about 8 nm,
wherein the second height is between about 5 nm and about 15 nm.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the second gate structure does not completely wrap around each of the second nanostructures.

### Claim 10

A semiconductor device, comprising:
a first transistor comprising:
a first nanostructure over and spaced apart from a first base portion, and
a first gate structure wrapping around the first nanostructure; and
a second transistor comprising:
a second nanostructure over and spaced apart from a second base portion, and
a second gate structure disposed over the second nanostructure
wherein the first nanostructure has a first width and a first height smaller than the first width,
wherein the second nanostructure has a second width and a second height greater than the second width,
wherein the first nanostructure extends lengthwise between a first source/drain feature and a second source/drain feature along a direction,
wherein the first nanostructure includes a channel portion directly under the first gate structure and a connection portion between the channel portion and the first source/drain feature along the direction, and
wherein a height of the connection portion is greater than a height of the channel portion.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein a width of the first base portion is greater than a width of the second base portion.

### Claim 12 (depends on 10)

The semiconductor device of claim 10, wherein the first width is greater than the second width.

### Claim 13 (depends on 10)

The semiconductor device of claim 10, wherein the first height is smaller than the second height.

### Claim 14 (depends on 10)

The semiconductor device of claim 10, further comprising
a gate spacer layer disposed along sidewalls of the first gate structure and sidewalls of the second gate structure.

### Claim 15 (depends on 10)

The semiconductor device of claim 10, wherein the second gate structure does not completely wrap around the second nanostructure.

### Claim 16

A method, comprising:
depositing, on a substrate, a stack comprising a plurality of silicon layers interleaved by a plurality of silicon germanium layers;
patterning the stack and the substrate into a first fin-shaped structure and a second fin-shaped structure extending lengthwise along a first direction;
forming a first dummy gate stack over a first channel region of the first fin-shaped structure and a second dummy gate stack over a second channel region of the second fin-shaped structure;
removing the first dummy gate stack and the second dummy gate stack;
selectively removing the silicon germanium layers in the first channel region and the second channel region to form first nanostructures in the first channel region and second nanostructures in the second channel region;
selectively trimming the first nanostructures in the first channel region while the second nanostructures are covered in a masking layer;
forming a first gate structure over the first nanostructures; and
forming a second gate structure over the second nanostructures,
wherein a width of the first fin-shaped structure along a second direction perpendicular to the first direction is greater than the second fin-shaped structure along the second direction.

### Claim 17 (depends on 16)

The method of claim 16,
wherein each of the first nanostructures has a first width and a first height smaller than the first width, and
wherein each of the second nanostructures has a second width and a second height greater than the second width.

### Claim 18 (depends on 17)

The method of claim 17, wherein the first width is greater than the second width.

### Claim 19 (depends on 17)

The method of claim 17, wherein the first height is smaller than the second height.

### Claim 20 (depends on 10)

The semiconductor device of claim 10, wherein a number of the first nanostructures is identical to a number of the second nanostructures.