# US 11,908,941 B2 · FinFET transistor

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- Number: US 11,908,941 B2
- Document ID: US11908941B2
- Status: Granted
- Kind: B2
- Application number: 17/551,712
- Filed: 2021-12-15
- Published: 2022-04-07
- Granted: 2024-02-20
- Earliest claimed: 2014-12-15
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Sang U. Kim; Kuhwan Kim
- Web page: https://patentgrep.com/patent/US11908941B2

## CPC

- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6212: {having fin-shaped semiconductor bodies having non-rectangular cross-sections}
- H10D 30/6213: {having rounded corners}
- H10D 30/6217: {having non-uniform gate electrodes, e.g. gate conductors having varying doping}
- H10D 30/67: Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)}
- H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes a semiconductor substrate having isolation regions formed therein and a fin-shaped semiconductor structure protruding vertically above the isolation regions and extending laterally in a first direction. The device additionally includes a gate dielectric wrapping a channel region of the fin-shaped semiconductor structure and a gate electrode wrapping the gate dielectric. The channel region is interposed in the first direction between a source region and a drain region and has sloped sidewalls and a width that continuously decreases from a base towards a peak of the channel region. The channel region comprises a volume inversion region having a height greater than about 25% of a total height of the channel region.

## Claims

### Claim 1

A semiconductor device, comprising:
a semiconductor substrate having isolation regions formed therein;
a fin structure disposed over the semiconductor substrate protruding vertically above the isolation regions and extending laterally in a first direction;
a gate structure disposed over the fin structure, the gate structure including a gate electrode and a gate dielectric; and
a channel region of the fin structure interposed in the first direction between a source region and a drain region,
wherein the channel region comprises an undoped volume inversion region having a shape such that no surface inversion occurs therein when an inversion bias is applied to the gate electrode, wherein the inversion bias is sufficient to form a surface inversion layer when applied to a bulk semiconductor material of the fin structure.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the semiconductor substrate is not a silicon-on-insulator (SOI) substrate.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the fin structure comprises a plurality of fin-shaped semiconductor structures between the source region and the drain region,
wherein the gate structure covers sidewalls of the plurality of fin-shaped semiconductor structures.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein a carrier concentration of the undoped volume inversion region is between about 1.5×1010/cm3 and about 1.0×1012/cm3.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the fin structure includes a sidewall having an angle between about 80 degrees and about 88 degrees relative to the isolation regions.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the conduction and valence band energies (EC, EV) of all portion of the volume inversion region is less than the conduction and valence band energies (EC,BULK, EV,BULK) of the bulk semiconductor material.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein a width of the channel region is between about 4 nm and about 8 nm.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the gate dielectric comprises a high K dielectric.

### Claim 9

A semiconductor device, comprising:
a semiconductor substrate having isolation regions formed therein;
a fin-shaped semiconductor structure protruding vertically above the isolation regions and extending laterally in a first direction, wherein the fin-shaped semiconductor structure forms a continuous extension of a bulk semiconductor substrate without having a buried oxide layer below the fin-shaped semiconductor structure; and
a gate dielectric directly overlying a channel region of the fin-shaped semiconductor structure and a gate electrode directly overlying the gate dielectric, the channel region being interposed in the first direction between a source region and a drain region,
wherein the channel region has sloped sidewalls and a width that continuously decreases from a base towards a peak of the channel region,
wherein the channel region comprises an undoped volume inversion region having a height greater than about 25% of a total height of the channel region, and
wherein the volume inversion region comprises a region in which, under an inversion condition, surface depletion regions extending from the opposing sloped sidewalls overlap,
wherein the volume inversion region includes an undoped region.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein a carrier concentration of the undoped volume inversion region is between about 1.5×1010/cm3 and about 1.0×1012/cm3.

### Claim 11 (depends on 9)

The semiconductor device of claim 9, wherein the fin-shaped semiconductor structure includes a sidewall having an angle between about 80 degrees and about 88 degrees relative to the isolation regions.

### Claim 12 (depends on 9)

The semiconductor device of claim 9, wherein the conduction and valence band energies (EC, EV) of all portion of the volume inversion region is less than the conduction and valence band energies (EC,BULK, EV,BULK) of the bulk semiconductor material.

### Claim 13 (depends on 9)

The semiconductor device of claim 9, wherein the gate dielectric comprises a high K dielectric.

### Claim 14 (depends on 9)

The semiconductor device of claim 9, wherein a width of the channel region is between about 4 nm and about 8 nm.

### Claim 15

A semiconductor device, comprising:
a semiconductor substrate having isolation regions formed therein;
a fin structure disposed over the semiconductor substrate protruding vertically above the isolation regions and extending laterally in a first direction; and
a gate structure disposed over the fin structure, the gate structure including a gate electrode and a gate dielectric;
wherein the fin structure includes a channel region between a source region and a drain region,
wherein the channel region comprises an undoped volume inversion region,
wherein the total height of the channel region does not exceed 34 nm.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the volume inversion region has a height extending downwardly from the apex of the fin-shaped semiconductor structure, the height being greater than about 25% of a total height of the channel region.

### Claim 17 (depends on 15)

The semiconductor device of claim 15, wherein a carrier concentration of the undoped volume inversion region is between about 1.5×1010/cm3 and about 1.0×1012/cm3.

### Claim 18 (depends on 15)

The semiconductor device of claim 15, wherein the channel region has sloped sidewalls and a width that continuously decreases from a base towards a peak of the channel region.

### Claim 19 (depends on 15)

The semiconductor device of claim 15, wherein the conduction and valence band energies (EC, EV) of all portion of the volume inversion region is less than the conduction and valence band energies (EC,BULK, EV,BULK) of the bulk semiconductor material.

### Claim 20 (depends on 15)

The semiconductor device of claim 15, wherein the gate dielectric comprises a high K dielectric.