# US 11,908,937 B2 · Vertical transport field-effect transistor with ring-shaped wrap-around contact

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- Number: US 11,908,937 B2
- Document ID: US11908937B2
- Status: Granted
- Kind: B2
- Application number: 17/376,752
- Filed: 2021-07-15
- Published: 2023-01-19
- Granted: 2024-02-20
- Earliest claimed: 2021-07-15
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Xin Miao; Kangguo Cheng; Chen Zhang; Wenyu Xu
- Web page: https://patentgrep.com/patent/US11908937B2

## CPC

- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/795: {being in lateral device isolation regions, e.g. STI}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 64/2527: {for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/016: {the components including vertical IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/837: {comprising vertical IGFETs}
- H10B 10/12: {comprising a MOSFET load element}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 30/6728: {Vertical TFTs}
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0195: {the components including vertical IGFETs}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Vertical transport field-effect transistors are formed on active regions wherein the active regions each include a wrap-around metal silicide contact on vertically extending side walls of the active region. Such wrap-around contacts form self-aligned and reliable strapping for SRAM bottom nFET and pFET source/drain regions. Buried contacts of SRAM cells may be used to strap the wrap-around metal silicide contacts with the gates of inverters thereof. Wrap-around metal silicide contacts provide additional contacts for logic FETs and reduce parasitic bottom source/drain resistance.

## Claims

### Claim 1

A semiconductor structure comprising:
a semiconductor substrate;
one or more active regions on the semiconductor substrate, each of the one or more active regions comprising:
a plurality of vertical transport field-effect transistors extending vertically with respect to the semiconductor substrate;
merged, bottom source/drain regions for the plurality of the vertical transport field-effect transistors; and
a peripheral side wall extending downwardly from a top surface of the merged, bottom source/drain regions and comprising a metal silicide contact wrapping around the merged bottom source/drain regions; and
shallow trench isolation regions surrounding, respectively, each of the one or more active regions and wherein the shallow trench isolation regions comprise:
a first dielectric liner adjoining the substrate and bottom portions of the peripheral side walls of the active regions;
a first layer of STI dielectric material within the first dielectric liner;
a second dielectric liner on a top surface of the first layer of STI dielectric material and adjoining the metal silicide contact; and
a second layer of STI dielectric material within the second dielectric liner.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, further including a metal contact contacting the metal silicide contact.

### Claim 3 (depends on 2)

The semiconductor structure of claim 2, wherein the metal contact adjoins a side wall surface of the metal silicide contact.

### Claim 4 (depends on 2)

The semiconductor structure of claim 2, further including:
an interlevel dielectric layer above the substrate and encasing portions of the vertical field-effect transistors; and wherein:
the metal contact comprises a buried contact within the interlevel dielectric layer;
the merged, bottom source/drain regions include a first source/drain region having n-type conductivity and a second source/drain region having p-type conductivity; and
the buried contact electrically straps the metal silicide contact of a first active region with a gate of a vertical transport field-effect transistors of a second active region on the substrate.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, further including:
semiconductor fins extending from the semiconductor substrate and comprising channel regions of the vertical transport field-effect transistors;
a bottom spacer over the merged, bottom source/drain regions;
top spacers adjoining the semiconductor fins; and
epitaxial top source/drain regions on the semiconductor fins and above the top spacers.

### Claim 6 (depends on 1)

The semiconductor structure of claim 1, wherein:
the one or more active regions include first and second active regions, each of the first and second active regions including merged, bottom source/drain regions having n-type and p-type conductivity, respectively, and vertically extending side walls;
the vertical transport field-effect transistors include first and second sets of transistors, the first set of transistors comprising portions of the first active region and the second set of transistors comprising portions of the second active region, the first and second sets of transistors being configured as a static random access memory cell.

### Claim 7 (depends on 6)

The semiconductor structure of claim 6, further including:
an interlevel dielectric layer encasing portions of the first and second sets of transistors;
first and second buried contacts within the interlevel dielectric layer;
the first buried contact electrically strapping the metal silicide contact wrapped around the merged source/drain regions comprising the first active region with a gate of one of the second set of transistors, the first buried contact extending partially within one of the shallow trench isolation regions; and
the second buried contact electrically strapping the metal silicide contact wrapped around the merged source/drain regions comprising the second active region with a gate of one of the first set of transistors, the second buried contact extending partially within the one of the shallow trench isolation regions.