# US 11,908,934 B2 · Semiconductor device having doped epitaxial region and its methods of fabrication

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- Number: US 11,908,934 B2
- Document ID: US11908934B2
- Status: Granted
- Kind: B2
- Application number: 17/161,534
- Filed: 2021-01-28
- Published: 2021-05-27
- Granted: 2024-02-20
- Earliest claimed: 2009-12-21
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Anand S. Murthy; Daniel Bourne Aubertine; Tahir Ghani; Abhijit Jayant Pethe
- Web page: https://patentgrep.com/patent/US11908934B2

## CPC

- H10D 30/608: {having non-planar bodies, e.g. having recessed gate electrodes}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10P 14/24: using chemical vapour deposition [CVD]
- H10P 14/27: {using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials}
- H10P 14/2905: {Silicon, silicon germanium or germanium}
- H10P 14/2925: {Surface structures}
- H10P 14/3408: {Silicon carbide}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3442: {N-type}
- H10P 70/20: {Cleaning during device manufacture}
- H10D 30/6212: {having fin-shaped semiconductor bodies having non-rectangular cross-sections}
- H10D 64/01316: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. Ta, W, Mo or Al}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/665: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum (having lateral variation H10D64/671)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Embodiments of the present invention describe a epitaxial region on a semiconductor device. In one embodiment, the epitaxial region is deposited onto a substrate via cyclical deposition-etch process. Cavities created underneath the spacer during the cyclical deposition-etch process are backfilled by an epitaxial cap layer. The epitaxial region and epitaxial cap layer improves electron mobility at the channel region, reduces short channel effects and decreases parasitic resistance.

## Claims

### Claim 1

A semiconductor structure, comprising:
a gate electrode over a single crystalline silicon substrate, the gate electrode defining a channel region in the single crystalline silicon substrate;
a gate dielectric between the gate electrode and the channel region, the gate dielectric having a bottom surface;
an epitaxial semiconductor source region laterally adjacent a first end of the channel region at a first side of the gate electrode and extending above an uppermost surface of the channel region, the epitaxial semiconductor source region in contact with a first portion of the bottom surface of the gate dielectric, and the epitaxial semiconductor source region comprising a first inflection point at a lowermost horizontal surface of the epitaxial semiconductor source region and a second inflection point above the first inflection point, wherein a single facet is between the first and second inflection points of the epitaxial semiconductor source region, wherein the first inflection point of the epitaxial semiconductor source region is not vertically beneath the gate electrode, and wherein the second inflection point of the epitaxial semiconductor source region is vertically beneath the gate electrode;
an epitaxial semiconductor drain region laterally adjacent a second end of the channel region at a second side of the gate electrode opposite the first side of the gate electrode and extending above an uppermost surface of the channel region, the epitaxial semiconductor drain region in contact with a second portion of the bottom surface of the gate dielectric, and the epitaxial semiconductor drain region comprising a first inflection point at a lowermost horizontal surface of the epitaxial semiconductor drain region and a second inflection point above the first inflection point, wherein a single facet is between the first and second inflection points of the epitaxial semiconductor drain region, wherein the first inflection point of the epitaxial semiconductor drain region is not vertically beneath the gate electrode, and wherein the second inflection point of the epitaxial semiconductor drain region is vertically beneath the gate electrode;
a first dielectric spacer adjacent the first side of the gate electrode and over a portion of the epitaxial semiconductor source region, wherein the first inflection point of the epitaxial semiconductor source region is not vertically beneath the first dielectric spacer; and
a second dielectric spacer adjacent the second side of the gate electrode and over a portion of the epitaxial semiconductor drain region, wherein the first inflection point of the epitaxial semiconductor drain region is not vertically beneath the second dielectric spacer.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the gate dielectric comprises a layer of hafnium oxide.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, wherein the gate electrode is a metal gate electrode.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, wherein the first dielectric spacer and the second dielectric spacer comprise silicon nitride.

### Claim 5

A method of fabricating a semiconductor structure, the method comprising:
forming a gate electrode over a single crystalline silicon substrate, the gate electrode defining a channel region in the single crystalline silicon substrate;
forming a gate dielectric between the gate electrode and the channel region, the gate dielectric having a bottom surface;
forming an epitaxial semiconductor source region laterally adjacent a first end of the channel region at a first side of the gate electrode and extending above an uppermost surface of the channel region, the epitaxial semiconductor source region in contact with a first portion of the bottom surface of the gate dielectric, and the epitaxial semiconductor source region comprising a first inflection point at a lowermost horizontal surface of the epitaxial semiconductor source region and a second inflection point above the first inflection point, wherein a single facet is between the first and second inflection points of the epitaxial semiconductor source region, wherein the first inflection point of the epitaxial semiconductor source region is not vertically beneath the gate electrode, and wherein the second inflection point of the epitaxial semiconductor source region is vertically beneath the gate electrode;
forming an epitaxial semiconductor drain region laterally adjacent a second end of the channel region at a second side of the gate electrode opposite the first side of the gate electrode and extending above an uppermost surface of the channel region, the epitaxial semiconductor drain region in contact with a second portion of the bottom surface of the gate dielectric, and the epitaxial semiconductor drain region comprising a first inflection point at a lowermost horizontal surface of the epitaxial semiconductor drain region and a second inflection point above the first inflection point, wherein a single facet is between the first and second inflection points of the epitaxial semiconductor drain region, wherein the first inflection point of the epitaxial semiconductor drain region is not vertically beneath the gate electrode, and wherein the second inflection point of the epitaxial semiconductor drain region is vertically beneath the gate electrode;
forming a first dielectric spacer adjacent the first side of the gate electrode and over a portion of the epitaxial semiconductor source region, wherein the first inflection point of the epitaxial semiconductor source region is not vertically beneath the first dielectric spacer; and
forming a second dielectric spacer adjacent the second side of the gate electrode and over a portion of the epitaxial semiconductor drain region, wherein the first inflection point of the epitaxial semiconductor drain region is not vertically beneath the second dielectric spacer.

### Claim 6 (depends on 5)

The method of claim 5, wherein the gate dielectric comprises a layer of hafnium oxide.

### Claim 7 (depends on 5)

The method of claim 5, wherein the gate electrode is a metal gate electrode.

### Claim 8 (depends on 5)

The method of claim 5, wherein the first dielectric spacer and the second dielectric spacer comprise silicon nitride.