# US 11,908,930 B2 · Laterally-diffused metal-oxide-semiconductor devices with a multiple-thickness buffer dielectric layer

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- Number: US 11,908,930 B2
- Document ID: US11908930B2
- Status: Granted
- Kind: B2
- Application number: 17/404,165
- Filed: 2021-08-17
- Published: 2023-02-23
- Granted: 2024-02-20
- Earliest claimed: 2021-08-17
- Assignees: Globalfoundries Singapore Pte. Ltd.
- Applicants: GLOBALFOUNDRIES Singapore Pte. Ltd.
- Inventors: Namchil Mun; Shiang Yang Ong
- Web page: https://patentgrep.com/patent/US11908930B2

## CPC

- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10P 90/1906: {Preparing SOI wafers}
- H10D 30/0281: {of lateral DMOS [LDMOS] FETs}
- H10D 62/109: {Reduced surface field [RESURF] PN junction structures}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10P 14/6308: {of Group IV semiconductors}
- H10P 14/6322: {Formation by thermal treatments (formation by plasma treatment H10P14/6319)}
- H10P 30/22: using masks
- H10W 10/012: {using local oxidation of silicon [LOCOS]}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/061: {using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations}
- H10W 10/13: formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Structures for a laterally-diffused metal-oxide-semiconductor device and methods of forming a structure for a laterally-diffused metal-oxide-semiconductor device. The structure includes a drift well in a semiconductor substrate, source and drain regions in the semiconductor substrate, a gate dielectric layer on the semiconductor substrate, and a buffer dielectric layer on the semiconductor substrate over the drift well. The buffer dielectric layer includes a first side edge adjacent to the drain region, a second side edge adjacent to the gate dielectric layer, a first section extending from the second side edge to the first side edge, and a plurality of second sections extending from the second side edge toward the first side edge. The first section has a first thickness, and the second sections have a second thickness less than the first thickness. A gate electrode includes respective portions that overlap with the buffer dielectric layer and with the gate dielectric layer.

## Claims

### Claim 1

A structure for a laterally-diffused metal-oxide-semiconductor device, the structure comprising:
a semiconductor substrate;
a drift well in the semiconductor substrate;
a source region and a drain region in the semiconductor substrate;
a gate dielectric layer on the semiconductor substrate;
a buffer dielectric layer on the semiconductor substrate over the drift well, the buffer dielectric layer including a first side edge adjacent to the drain region, a second side edge that abuts the gate dielectric layer, a first section extending from the second side edge to the first side edge, and a plurality of second sections extending from the second side edge toward the first side edge, the first section having a first thickness, and each of the second sections having a second thickness less than the first thickness; and
a gate electrode laterally positioned between the source region and the drain region, the gate electrode including a first portion that overlaps with the buffer dielectric layer and a second portion that overlaps with the gate dielectric layer,
wherein the plurality of second sections of the buffer dielectric layer alternate with portions of the first section of the buffer dielectric layer along the second side edge.

### Claim 2 (depends on 1)

The structure of claim 1 wherein the gate electrode fully overlaps with the second sections of the buffer dielectric layer.

### Claim 3 (depends on 1)

The structure of claim 1 wherein the gate electrode partially overlaps with the second sections of the buffer dielectric layer.

### Claim 4 (depends on 1)

The structure of claim 1 wherein each of the second sections is joined to the first section of the buffer dielectric layer by a third section, and the third section tapers has a third thickness that tapers from the first thickness to the second thickness.

### Claim 5 (depends on 1)

The structure of claim 1 wherein the gate dielectric layer has a third thickness that is less than the first thickness and less than the second thickness.

### Claim 6 (depends on 1)

The structure of claim 1 wherein the first section separates the second sections from the drain region.

### Claim 7 (depends on 1)

The structure of claim 1 further comprising:
a doped region in the drift well, the doped region positioned beneath the first section of the buffer di electric layer,
wherein the drift well is doped to have a first conductivity type, and the doped region is doped to have a second conductivity type different than the first conductivity type.

### Claim 8 (depends on 7)

The structure of claim 7 wherein the doped region is coextensive with the first section of the buffer dielectric layer.

### Claim 9 (depends on 7)

The structure of claim 7 wherein the drift well is coextensive with the second sections of the buffer dielectric layer.

### Claim 10 (depends on 7)

The structure of claim 7 wherein the doped region is absent beneath the second sections of the buffer dielectric layer.

### Claim 11 (depends on 1)

The structure of claim 1 wherein the second side edge of the buffer dielectric layer abuts the gate dielectric layer.

### Claim 12 (depends on 11)

The structure of claim 11 wherein the gate dielectric layer is positioned between the second side edge of the buffer dielectric layer and the source region.

### Claim 13 (depends on 1)

The structure of claim 1 wherein the buffer dielectric layer comprises silicon dioxide.

### Claim 14

A method of forming a structure for a laterally-diffused metal-oxide-semiconductor device, the method comprising:
forming a drift well in a semiconductor substrate;
forming a source region and a drain region in the semiconductor substrate;
forming a gate dielectric layer on the semiconductor substrate;
forming a buffer dielectric layer on the semiconductor substrate over the drift well; and
forming a gate electrode laterally positioned between the source region and the drain region,
wherein the buffer dielectric layer includes a first side edge adjacent to the drain region, a second side edge adjacent to the gate dielectric layer, a first section extending from the second side edge to the first side edge, and a plurality of second sections extending from the second side edge toward the first side edge, the first section has a first thickness, each of the second sections has a second thickness less than the first thickness, and the gate electrode includes a first portion that overlaps with the buffer dielectric layer and a second portion that overlaps with the gate dielectric layer, and
wherein forming the buffer dielectric layer on the semiconductor substrate over the drift well comprises:
forming a hardmask on the semiconductor substrate with an opening shaped to provide the first section and the second sections that are formed by a thermal oxidation process with the hardmask on the semiconductor substrate.

### Claim 15 (depends on 14)

The method of claim 14 wherein the hardmask includes a plurality of notches that alternate with a plurality of projections along a side edge.

### Claim 16 (depends on 14)

The method of claim 14 further comprising:
forming a doped region in the drift well that is positioned beneath the first section of the buffer dielectric layer,
wherein the drift well is doped to have a first conductivity type, the doped region is doped to have a second conductivity type different than the first conductivity type, the doped region is coextensive with the first section of the buffer dielectric layer, and the drift well is coextensive with the second sections of the buffer dielectric layer.

### Claim 17 (depends on 16)

The method of claim 16 wherein the doped region is absent beneath the second sections of the buffer dielectric layer.

### Claim 18 (depends on 14)

The method of claim 14 wherein the gate electrode fully overlaps with the second sections of the buffer dielectric layer.

### Claim 19 (depends on 15)

The method of claim 15 wherein the notches and the projections have dimensions selected to provide the second thickness of the second sections.

### Claim 20 (depends on 19)

The method of claim 19 wherein the notches are rectangular, and the projections are rectangular.