# US 11,908,929 B2 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,908,929 B2 - Document ID: US11908929B2 - Status: Granted - Kind: B2 - Application number: 17/974,130 - Filed: 2022-10-26 - Published: 2023-02-16 - Granted: 2024-02-20 - Earliest claimed: 2020-06-26 - Assignees: Fuji Electric Co., Ltd. - Applicants: Fuji Electric Co., Ltd. - Inventors: Keiji Okumura - Web page: https://patentgrep.com/patent/US11908929B2 ## CPC - H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors} - H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes} - H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)} - H10D 62/8325: {Silicon carbide} - H10D 64/664: {the additional layers comprising a barrier layer between the layer of silicon and an upper metal or metal silicide layer} - H10D 62/157: {Impurity concentrations or distributions} - H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)} - H10D 64/519: {characterised by their top-view geometrical layouts} - H10D 64/62: Electrodes ohmically coupled to a semiconductor - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor device having an active portion and a gate pad portion on a semiconductor substrate includes: a first semiconductor layer of a first conductivity type; and a second semiconductor layer of a second conductivity type. The active portion has: first semiconductor regions of the first conductivity type; a first electrode provided on the first semiconductor regions; and first trenches. The gate pad portion has: a gate electrode pad provided above the second semiconductor layer; second trenches provided beneath the gate electrode pad; and second semiconductor regions of the second conductivity type, each provided in the first semiconductor layer so as to be in contact with a respective one of bottoms of the second trenches. Each of the second trenches is continuous with a respective one of the first trenches. The second semiconductor layer is continuous from the active portion to the gate pad portion. ## Claims ### Claim 1 A semiconductor device having an active portion and a gate pad portion on a semiconductor substrate, the semiconductor device comprising: a first semiconductor layer of a first conductivity type, the first semiconductor layer having a first surface and a second surface opposite to each other; a second semiconductor layer of a second conductivity type, provided on the first surface of the first semiconductor layer, the second semiconductor layer having a first surface and a second surface opposite to each other, the second surface of the second semiconductor layer facing the first semiconductor layer; in the active portion: a plurality of first semiconductor regions of the first conductivity type, selectively provided in the second semiconductor layer at the first surface thereof; a first electrode provided on the first semiconductor regions; and a plurality of first trenches penetrating through the first semiconductor regions and the second semiconductor layer and reaching the first semiconductor layer, the first trenches extending in beneath the first electrode in an extending direction that is parallel to the first surface of the first semiconductor layer; in the gate pad portion: a gate electrode pad provided above the second semiconductor layer; a plurality of second trenches provided beneath the gate electrode pad, the second trenches extending in the extending direction; and a plurality of second semiconductor regions of the second conductivity type, each provided in the first semiconductor layer so as to be in contact with a respective one of bottoms of the second trenches; and one or more third semiconductor regions of the second conductivity type, each of which is provided in the first semiconductor layer so as to be in contact with a corresponding one of two opposing sidewalls of the second trenches, and electrically connects the second semiconductor layer and a corresponding one of the second semiconductor regions, wherein each of the second trenches is continuous with a respective one of the first trenches, and the second semiconductor layer is continuous from the active portion to the gate pad portion. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the one or more third semiconductor regions are provided at both of the sidewalls of a corresponding one of the second trenches. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein the one or more third semiconductor regions includes a plurality of third semiconductor regions, provided along the extending direction in the first semiconductor layer so as to be in contact with the corresponding one of the sidewalls of the second trenches. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein a respective one of the one or more third semiconductor regions is continuously in contact with a respective one of the sidewalls of the second trenches. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, further comprising a plurality of fourth semiconductor regions of the second conductivity type, each of which is provided in the first semiconductor layer so as to be in contact with a respective one of bottoms of the first trenches. ### Claim 6 (depends on 1) The semiconductor device according to claim 1, wherein the gate electrode pad is disposed between portions of the first electrode in the extending direction, in a plan view of the semiconductor device. ### Claim 7 (depends on 1) The semiconductor device according to claim 1, wherein both of opposite ends of each of the second trenches are each continuous with a respective one of the first trenches. ### Claim 8 (depends on 1) The semiconductor device according to claim 1, further comprising a wire connected to the gate electrode pad. ### Claim 9 (depends on 8) The semiconductor device according to claim 8, wherein the wire extends substantially in the extending direction. ### Claim 10 (depends on 1) The semiconductor device according to claim 1, further comprising a plurality of second electrodes respectively provided in the plurality of first trenches via a first insulating film; a plurality of third electrodes respectively provided in the plurality of second trenches via a second insulating film; and an interlayer insulating film provided on the third electrodes in the gate pad portion. ### Claim 11 (depends on 10) The semiconductor device according to claim 10, wherein the interlayer insulating film is provided directly beneath the gate electrode pad. ### Claim 12 (depends on 10) The semiconductor device according to claim 10, wherein each of the plurality second electrodes and each of the plurality of third electrodes are gate electrodes. ### Claim 13 (depends on 10) The semiconductor device according to claim 10, wherein each of the plurality of second electrodes and each of the plurality of third electrodes are polycrystalline silicon films. ### Claim 14 (depends on 10) The semiconductor device according to claim 10, wherein each of plurality of second electrodes and each of the plurality of third electrodes contains a refractory metal. ### Claim 15 (depends on 10) The semiconductor device according to claim 10, wherein the interlayer insulating film is free of a contact hole in the gate pad portion. ### Claim 16 A semiconductor device having an active portion and a gate pad portion on a semiconductor substrate, the semiconductor device comprising: a first semiconductor layer of a first conductivity type, the first semiconductor layer having a first surface and a second surface opposite to each other; a second semiconductor layer of a second conductivity type, provided on the first surface of the first semiconductor layer, the second semiconductor layer having a first surface and a second surface opposite to each other, the second surface of the second semiconductor layer facing the first semiconductor layer; in the active portion: a plurality of first semiconductor regions of the first conductivity type, selectively provided in the second semiconductor layer at the first surface thereof; a first electrode provided on the first semiconductor regions; and a plurality of first trenches penetrating through the first semiconductor regions and the second semiconductor layer and reaching the first semiconductor layer, the first trenches extending in beneath the first electrode in an extending direction that is parallel to the first surface of the first semiconductor layer; in the gate pad portion: a gate electrode pad provided above the second semiconductor layer; a plurality of second trenches provided beneath the gate electrode pad, the second trenches extending in the extending direction; and a plurality of second semiconductor regions of the second conductivity type, each provided in the first semiconductor layer so as to be in contact with a respective one of bottoms of the second trenches; and a plurality of fourth semiconductor regions of the second conductivity type, each of which is provided in the first semiconductor layer so as to be in contact with a respective one of bottoms of the first trenches, wherein each of the second trenches is continuous with a respective one of the first trenches, the second semiconductor layer is continuous from the active portion to the gate pad portion, and each of the fourth semiconductor regions is continuous with a respective one of the second semiconductor regions. ### Claim 17 A semiconductor device having an active portion and a gate pad portion on a semiconductor substrate, the semiconductor device comprising: a first semiconductor layer of a first conductivity type, the first semiconductor layer having a first surface and a second surface opposite to each other; a second semiconductor layer of a second conductivity type, provided on the first surface of the first semiconductor layer, the second semiconductor layer having a first surface and a second surface opposite to each other, the second surface of the second semiconductor layer facing the first semiconductor layer; in the active portion: a plurality of first semiconductor regions of the first conductivity type, selectively provided in the second semiconductor layer at the first surface thereof; a first electrode provided on the first semiconductor regions; and a plurality of first trenches penetrating through the first semiconductor regions and the second semiconductor layer and reaching the first semiconductor layer, the first trenches extending in beneath the first electrode in an extending direction that is parallel to the first surface of the first semiconductor layer; in the gate pad portion: a gate electrode pad provided above the second semiconductor layer; a plurality of second trenches provided beneath the gate electrode pad, the second trenches extending in the extending direction; and a plurality of second semiconductor regions of the second conductivity type, each provided in the first semiconductor layer so as to be in contact with a respective one of bottoms of the second trenches; a plurality of fourth semiconductor regions of the second conductivity type, each of which is provided in the first semiconductor layer so as to be in contact with a respective one of bottoms of the first trenches; and one or more fifth semiconductor regions of the second conductivity type, each of which is provided in the first semiconductor layer so as to be in contact with a corresponding one of two opposing sidewalls of the first trenches, and electrically connects the second semiconductor layer and a corresponding one of the fourth semiconductor regions, wherein each of the second trenches is continuous with a respective one of the first trenches, and the second semiconductor layer is continuous from the active portion to the gate pad portion. ### Claim 18 (depends on 17) The semiconductor device according to claim 17, wherein the one or more fifth semiconductor regions includes a plurality of fifth semiconductor regions, provided along the extending direction in the first semiconductor layer so as to be in contact with the corresponding one of the sidewalls of the first trenches.