# US 11,908,925 B2 · Semiconductor device and method for controlling semiconductor device

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 11,908,925 B2
- Document ID: US11908925B2
- Status: Granted
- Kind: B2
- Application number: 17/468,239
- Filed: 2021-09-07
- Published: 2022-10-13
- Granted: 2024-02-20
- Earliest claimed: 2021-04-09
- Assignees: Kabushiki Kaisha Toshiba; Toshiba Electronic Devices & Storage Corporation
- Applicants: Kabushiki Kaisha Toshiba; Toshiba Electronic Devices & Storage Corporation
- Inventors: Yoko Iwakaji; Tomoko Matsudai; Hiroko Itokazu; Keiko Kawamura
- Web page: https://patentgrep.com/patent/US11908925B2

## CPC

- H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs}
- H03K 17/567: Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
- H10D 62/133: {Emitter regions of BJTs}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates}
- H10D 64/281: {Base electrodes for bipolar transistors}
- H10D 64/519: {characterised by their top-view geometrical layouts}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A semiconductor device includes a first electrode, a second electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, a fourth semiconductor region, a fifth semiconductor region, a first gate electrode, and a second gate electrode. The first gate electrode faces the second semiconductor region via a first insulating film. The second gate electrode faces the second semiconductor region via a second insulating film and faces the second electrode via a third insulating film contacting the second insulating film. The fifth semiconductor region includes a boundary portion that electrically contacts the second electrode. A distance between an upper surface of the fourth semiconductor region and the first electrode is greater than a distance between the boundary portion and the first electrode.

## Claims

### Claim 1

A semiconductor device, comprising:
a first electrode;
a second electrode separated from the first electrode in a first direction;
a first semiconductor region located between the first electrode and the second electrode in the first direction, the first semiconductor region being of a first conductivity type;
a second semiconductor region located between the first semiconductor region and the second electrode, the second semiconductor region being of a second conductivity type;
a third semiconductor region located between the first semiconductor region and the first electrode, the third semiconductor region being of the second conductivity type and being electrically connected with the first electrode;
a first gate electrode facing the second semiconductor region via a first insulating film in a second direction, the first gate electrode facing the second electrode via a third insulating film contacting the first insulating film, the second direction crossing the first direction, a plurality of the first gate electrodes being provided;
a second gate electrode facing the second semiconductor region via a second insulating film in the second direction, the second gate electrode facing the second electrode via the third insulating film contacting the second insulating film, a different voltage from the first gate electrode being applied to the second gate electrode, a plurality of the second gate electrodes being provided;
a fourth semiconductor region located between the second semiconductor region and the second electrode, the fourth semiconductor region being of the first conductivity type and being next to the first gate electrode with the first or third insulating film interposed; and
a fifth semiconductor region located between the second semiconductor region and the second electrode, the fifth semiconductor region being of the second conductivity type, being next to the second gate electrode with the second or third insulating film interposed, and including a boundary portion that electrically contacts the second electrode,
a distance between an upper surface of the fourth semiconductor region and the first electrode being greater than a distance between the boundary portion and the first electrode.

### Claim 2 (depends on 1)

The device according to claim 1, wherein
a second-conductivity-type impurity concentration of the fifth semiconductor region is greater than a second-conductivity-type impurity concentration of the second semiconductor region.

### Claim 3 (depends on 1)

The device according to claim 1, further comprising:
a first gate electrode pad electrically connected with the first gate electrode; and
a second gate electrode pad electrically connected with the second gate electrode.

### Claim 4 (depends on 1)

The device according to claim 1, wherein
the fifth semiconductor region positioned between a first one of the first gate electrodes and the first or second gate electrode next to the first one of the first gate electrodes contacts the second electrode with a contact area different from a contact area of the second electrode in contact with the fifth semiconductor region positioned between a second one of the first gate electrodes and the first or second gate electrode next to the second one of the first gate electrodes.

### Claim 5 (depends on 1)

The device according to claim 1, wherein
the second semiconductor region positioned between the first gate electrode and the first or second gate electrode next to the first gate electrode is electrically insulated from the second electrode.

### Claim 6 (depends on 1)

The device according to claim 1, wherein
at least one of the first gate electrodes of the plurality of first gate electrodes is electrically connected with the second electrode.

### Claim 7 (depends on 1)

The device according to claim 1, comprising:
a cell region including the first and second gate electrodes; and
a termination region surrounding the cell region,
the first gate electrode located at the termination region side in the second direction being connected to the second electrode,
the second gate electrode next to the first gate electrode connected to the second electrode being next to the fifth semiconductor region with the second insulating film interposed.

### Claim 8 (depends on 7)

The device according to claim 7, wherein
more of the second gate electrodes are provided in the cell region proximate to the termination region in the second direction than in the cell region distant to the termination region in the second direction.

### Claim 9 (depends on 1)

The device according to claim 1, comprising:
a cell region including the first and second gate electrodes; and
a termination region surrounding the cell region,
among a plurality of the second gate electrodes located in the cell region, a first distance between a first one of the second gate electrodes and a second one of the second gate electrodes being less than a second distance between a third one of the second gate electrodes and a fourth one of the second gate electrodes,
the first one of the second gate electrodes being most proximate to the termination region in the second direction,
the second one of the second gate electrodes being located next to the first one of the second gate electrodes,
the third one of the second gate electrodes being located between the second one of the second gate electrodes and a center of the cell region,
the fourth one of the second gate electrodes being located next to the third one of the second gate electrodes.

### Claim 10 (depends on 1)

A method for controlling the semiconductor device according to claim 1, the method comprising:
at a first timing, changing a first gate voltage applied to the first gate electrode from a voltage less than a threshold voltage to a voltage not less than the threshold voltage;
at a second timing continuing from the first timing, changing a second gate voltage applied to the second gate electrode from a first voltage to a second voltage; and
at a third timing continuing from the second timing, changing the first gate voltage from the voltage not less than the threshold voltage to a voltage less than the threshold voltage.

### Claim 11 (depends on 10)

The method according to claim 10, wherein
the second voltage is a negative voltage when the first conductivity type is an n-type, and
the second voltage is a positive voltage when the first conductivity type is a p-type.

### Claim 12 (depends on 10)

The method according to claim 10, wherein
the second voltage applied to the second gate electrode forms an inversion layer in the first semiconductor region contacting the second insulating film.