# US 11,908,923 B2 · Low-resistance top contact on VTFET

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- Number: US 11,908,923 B2
- Document ID: US11908923B2
- Status: Granted
- Kind: B2
- Application number: 17/026,451
- Filed: 2020-09-21
- Published: 2021-01-07
- Granted: 2024-02-20
- Earliest claimed: 2018-08-30
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Christopher J. Waskiewicz; Su Chen Fan; Hari Prasad Amanapu; Hemanth Jagannathan
- Web page: https://patentgrep.com/patent/US11908923B2

## CPC

- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/01: Manufacture or treatment
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 64/252: {for vertical or pseudo-vertical devices}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/076: {in via holes or trenches}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/054: {by selectively removing parts thereof (H10W20/034 takes precedence)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor includes a semiconductor substrate having a bottom source/drain region and a vertical semiconductor fin having a bottom end that contacts the semiconductor substrate. The semiconductor device further includes a top source/drain region on a top end of the vertical semiconductor. The top source/drain region is separated from the semiconductor substrate by the vertical semiconductor fin. The semiconductor device further includes an electrically conductive cap on an outer surface of the top source/drain region.

## Claims

### Claim 1

A method for forming a semiconductor device, the method comprising:
forming a bottom source/drain region on a semiconductor substrate;
forming a vertical semiconductor fin including a bottom end that contacts the semiconductor substrate and is in electrical communication with the bottom source/drain region;
forming a gate structure that wraps completely around all sidewalls the vertical semiconductor fin, wherein a top end of the vertical semiconductor fin extends above the gate structure;
depositing an interlayer dielectric (ILD) on an upper surface of the substrate and subsequently patterning the ILD layer to form a patterned trench that expose the top end of the vertical semiconductor fin;
forming a top source/drain region by epitaxially growing silicon within the patterned trench and from the top end of the vertical semiconductor fin and on sidewalls of the vertical semiconductor fin, the top source/drain region formed directly on an upper surface of the gate structure separated from the semiconductor substrate by the vertical semiconductor fin;
forming an electrically conductive cap within the patterned trench and on an outer surface of the top source/drain region; and
forming an electrically conductive contact via in ohmic connection with the electrically conductive cap to establish an electrically conductive path from the contact via to the bottom source/drain region,
wherein forming an electrically conductive cap within the patterned trench comprises:
depositing an electrically conductive film directly on sidewalls and a base of the patterned trench, and directly on exposed surfaces of the top source/drain region;
depositing a dielectric material in the patterned trench so as to encapsulate the electrically conductive film deposited in the trench and on the top source/drain region with the dielectric material; and
performing a temperature anneal process that converts the electrically conductive film formed on the top source/drain region into the electrically conductive cap that is encapsulated by the dielectric material.

### Claim 2 (depends on 1)

The method of claim 1, wherein the temperature anneal process converts the electrically conductive film into a binary compound of a semiconductor material included in the top source/drain region.

### Claim 3 (depends on 2)

The method of claim 2, wherein the electrically conductive film is converted to a silicide material that defines the conductive cap.

### Claim 4 (depends on 3)

The method of claim 3, wherein forming the electrically conductive contact via comprises:
encapsulating the electrically conductive cap with a dielectric material;
selectively forming a top source/drain (TSD) trench that extends through the dielectric material and stops on the electrically conductive cap; and
depositing an electrically conductive material in the TSD trench to establish ohmic connection with the electrically conductive cap.

### Claim 5 (depends on 4)

The method of claim 4, wherein the gate structure includes a bottom portion that directly contacts the semiconductor substrate and a top portion that directly contacts the top source/drain region.

### Claim 6 (depends on 5)

The method of claim 5, wherein gate structure is interposed between the semiconductor substrate and the electrically conductive cap.

### Claim 7 (depends on 4)

The method of claim 4, wherein the TSD trench is formed after converting the electrically conductive film into the electrically conductive cap.