# US 11,908,922 B2 · Heterogeneous semiconductor device substrates with high quality epitaxy

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- Number: US 11,908,922 B2
- Document ID: US11908922B2
- Status: Granted
- Kind: B2
- Application number: 17/080,613
- Filed: 2020-10-26
- Published: 2021-02-25
- Granted: 2024-02-20
- Earliest claimed: 2017-11-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Carlos H. Diaz; Mark Van Dal; Martin Christopher Holland
- Web page: https://patentgrep.com/patent/US11908922B2

## CPC

- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 30/0223: {having source and drain regions or source and drain extensions self-aligned to sides of the gate}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/124: {Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions}
- H10D 62/405: {Orientations of crystalline planes}
- H10P 14/271: {characterised by the preparation of substrate for selective deposition}
- H10P 14/2905: {Silicon, silicon germanium or germanium}
- H10P 14/2925: {Surface structures}
- H10P 14/2926: {Crystal orientations}
- H10P 14/3211: {Silicon, silicon germanium or germanium}
- H10P 14/3414: {being group IIIA-VIA materials}
- H10P 14/36: {characterised by treatments done before the formation of the materials}
- H10P 50/642: {Chemical etching}
- H10P 50/644: {Anisotropic liquid etching (H10P50/61 takes precedence)}
- H10P 50/693: {characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane}
- H10D 62/834: further characterised by the dopants
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/21: {of electrically active species}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure includes a substrate, a first epitaxial layer, a second epitaxial layer, and a transistor. The substrate includes a first pyramid protrusion, a second pyramid protrusion, a third pyramid protrusion, and a fourth pyramid protrusion. The first and second pyramid protrusions are arranged along a first direction, the second and fourth pyramid protrusions are arranged along the first direction, and the first and third pyramid protrusions are arranged along a second direction crossing the first direction. The first epitaxial layer is over the substrate and in contact with the first, second, third, and fourth pyramid protrusions. The second epitaxial layer is over the first epitaxial layer. The transistor is over the second epitaxial layer.

## Claims

### Claim 1

A semiconductor structure, comprising:
a substrate comprising a first pyramid protrusion, a second pyramid protrusion, a third pyramid protrusion, and a fourth pyramid protrusion, wherein the first and second pyramid protrusions are arranged along a first direction, the second and fourth pyramid protrusions are arranged along the first direction, and the first and third pyramid protrusions are arranged along a second direction crossing the first direction, wherein a top surface of the first pyramid protrusion has a (100) crystal orientation;
a first epitaxial layer over the substrate and in contact with the first, second, third, and fourth pyramid protrusions, wherein the first epitaxial layer is a single piece of continuous material;
a second epitaxial layer over the first epitaxial layer, wherein the second epitaxial layer is a single piece of continuous material, and the first epitaxial layer is in contact with the substrate and the second epitaxial layer; and
a transistor over and partially embedded in the second epitaxial layer.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, further comprising an isolation structure embedded in the second epitaxial layer.

### Claim 3 (depends on 2)

The semiconductor structure of claim 2, wherein the isolation structure is spaced apart from the first epitaxial layer.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, wherein each of the first, second, third, and fourth pyramid protrusions has four (111) sidewalls.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, wherein each of the first, second, third, and fourth pyramid protrusions has a height in a range of about 5 nm to about 80 nm.

### Claim 6 (depends on 1)

The semiconductor structure of claim 1, wherein a top surface of the first epitaxial layer is flatter than a bottom surface of the first epitaxial layer.

### Claim 7 (depends on 1)

The semiconductor structure of claim 1, wherein a sidewall of the first pyramid protrusion and a sidewall of the second pyramid protrusion share an edge.

### Claim 8 (depends on 1)

The semiconductor structure of claim 1, wherein a sidewall of the first pyramid protrusion and a sidewall of the third pyramid protrusion share an edge.

### Claim 9 (depends on 1)

The semiconductor structure of claim 1, wherein a gate structure of the transistor is in contact with the second epitaxial layer.

### Claim 10

A method comprising:
forming a mask layer over a substrate;
patterning the mask layer to expose portions of the substrate;
etching the substrate by using the patterned mask layer as an etch mask to form a plurality of pyramid protrusions at a top surface of the substrate, wherein a top surface of one of the plurality of pyramid protrusions has a (100) crystal orientation;
removing the patterned mask layer;
forming a first epitaxial layer over and in contact with the plurality of pyramid protrusions of the substrate, wherein the first epitaxial layer is a single piece of continuous material;
forming a second epitaxial layer over the first epitaxial layer, wherein the second epitaxial layer is a single piece of continuous material, and the first epitaxial layer is in contact with the substrate and the second epitaxial layer; and
forming a transistor over and partially embedded in the second epitaxial layer.

### Claim 11 (depends on 10)

The method of claim 10, wherein patterning the mask layer comprises forming a plurality of dots arranged in rows and columns, and a diameter of each of the dots of the mask layer is substantially equal to a minimum distance directly between adjacent two of the dots of the mask layer.

### Claim 12 (depends on 10)

The method of claim 10, wherein an etchant used in the etching the substrate has a higher etch rate in a (100) crystal plane than in a (111) crystal plane.

### Claim 13 (depends on 10)

The method of claim 10, wherein an etchant used in the etching the substrate has a higher etch rate in a (110) crystal plane than in a (111) crystal plane.

### Claim 14 (depends on 10)

The method of claim 10, wherein the transistor is over the plurality of pyramid protrusions of the substrate.

### Claim 15

A method comprising:
forming a mask layer over a substrate;
forming a plurality of holes in the mask layer to expose the substrate, wherein a diameter of each of the holes is less than about 100 nm, and the diameter of each of the holes of the mask layer is substantially equal to a minimum width of a portion of the mask layer directly between adjacent two of the holes of the mask layer;
etching the substrate by using the mask layer as an etch mask such that a plurality of recesses are formed in the substrate;
forming a first epitaxial layer over the substrate and filling the recesses; and
forming a second epitaxial layer over the first epitaxial layer.

### Claim 16 (depends on 15)

The method of claim 15, wherein etching the substrate is performed such that the mask layer is removed.

### Claim 17 (depends on 15)

The method of claim 15, wherein the holes of the mask layer have substantially equal size.

### Claim 18 (depends on 15)

The method of claim 15, wherein etching the substrate is performed using at least one of potassium hydroxide (KOH) and tetramethyl-ammonium-hydroxide (TMAH).

### Claim 19 (depends on 15)

The method of claim 15, wherein the first epitaxial layer is lattice mismatched to the substrate.

### Claim 20 (depends on 15)

The method of claim 15, wherein the holes of the mask layer are arranged to form a first row and a second row in a top view, and the holes in the first row are offset from the holes in the second row.