# US 11,908,920 B2 · Fin field-effect transistor device and method of forming the same

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- Number: US 11,908,920 B2
- Document ID: US11908920B2
- Status: Granted
- Kind: B2
- Application number: 17/722,787
- Filed: 2022-04-18
- Published: 2022-07-28
- Granted: 2024-02-20
- Earliest claimed: 2019-10-31
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Shih-Yao Lin; Kuei-Yu Kao; Chih-Han Lin; Ming-Ching Chang; Chao-Cheng Chen
- Web page: https://patentgrep.com/patent/US11908920B2

## CPC

- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6217: {having non-uniform gate electrodes, e.g. gate conductors having varying doping}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 50/246: {of Group III-V materials}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate electrode over the fin; removing lower portions of the dummy gate electrode proximate to the isolation regions, where after removing the lower portions, there is a gap between the isolation regions and a lower surface of the dummy gate electrode facing the isolation regions; filling the gap with a gate fill material; after filling the gap, forming gate spacers along sidewalls of the dummy gate electrode and along sidewalls of the gate fill material; and replacing the dummy gate electrode and the gate fill material with a metal gate.

## Claims

### Claim 1

A semiconductor device comprising:
a fin protruding above a substrate;
isolation regions on opposing sides of the fin;
a gate structure over the fin, wherein the gate structure comprises a gate dielectric layer and a gate electrode over the gate dielectric layer;
gate spacers along opposing sidewalls of the gate structure, wherein a first width of a lower portion of the gate structure proximate to the isolation regions, measured between the gate spacers, decreases as the lower portion of the gate structure extends toward the isolation regions; and
a gate fill material along sidewalls of the lower portion of the gate structure, wherein the gate fill material is between the gate structure and the gate spacers, wherein the gate structure extends into the isolation regions, and is closer to the substrate than a lowest surface of the gate fill material facing the isolation regions.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein an upper portion of the gate structure, which is disposed over the lower portion of the gate structure, has a second width that remains the same as the upper portion of the gate structure extends toward the isolation regions.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the gate fill material is disposed on the isolation regions and contacts the isolation regions.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the gate fill material covers sidewalls of the lower portion of the gate structure and exposes sidewalls of an upper portion of the gate structure distal from the substrate.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein sidewalls of the gate fill material are aligned with respective sidewalls of the upper portion of the gate structure along same vertical lines.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the gate fill material extends along sidewalls of the gate structure from an upper surface of the gate structure distal from the substrate to a lower surface of the gate structure facing the substrate.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein an upper portion of the gate fill material distal from the isolation regions has a uniform thickness, and a lower portion of the gate fill material proximate to the isolation regions has a thickness that increases as the gate fill material extends toward the isolation regions.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the lowest surface of the gate fill material is a flat surface, wherein a lower surface of the gate structure facing the isolation regions is a curved surface.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the lowest surface of the gate fill material contacts the isolation regions.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, further comprising a dummy fin adjacent to the fin and extending parallel to the fin, wherein the gate structure is over the dummy fin and the fin.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the dummy fin is shorter than the fin.

### Claim 12

A semiconductor device comprising:
a substrate;
a fin protruding above the substrate;
isolation regions on opposing sides of the fin;
a gate structure over the fin, wherein the gate structure comprises a gate dielectric layer and a gate electrode over the gate dielectric layer;
gate spacers along opposing sidewalls of the gate structure; and
a gate fill material around the gate structure, wherein the gate fill material is disposed laterally between the gate spacers and the gate structure, and is disposed vertically between the gate structure and the isolation regions.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein a lower portion of the gate structure contacts the isolation regions, wherein the lower portion of the gate structure tapers off as the lower portion of the gate structure extends toward the isolation regions.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein the gate fill material contacts and extends along sidewalls of the lower portion of the gate structure.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein sidewalls of an upper portion of the gate structure are free of the gate fill material.

### Claim 16 (depends on 14)

The semiconductor device of claim 14, wherein the gate fill material further contacts and extends along sidewalls of an upper portion of the gate structure, wherein the gate spacers are separated from the gate structure by the gate fill material.

### Claim 17

A semiconductor device comprising:
a fin that protrudes above a substrate;
isolation regions on opposite sides of the fin;
a gate structure over the fin, wherein the gate structure comprises a gate dielectric layer and a gate electrode over the gate dielectric layer;
gate spacers along opposite sidewalls of the gate structure, wherein a lower portion of the gate structure extends into the isolation regions, wherein the lower portion of the gate structure tapers off as the gate structure extend toward the isolation regions; and
a gate fill material along sidewalls of the lower portion of the gate structure, wherein the gate fill material is between the gate spacers and the gate structure, wherein a width of the gate fill material along the sidewalls of the lower portion of the gate structure increases as the gate fill material extends toward the isolation regions.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein an upper portion of the gate structure distal from the substrate has a uniform width measured between the gate spacers.

### Claim 19 (depends on 18)

The semiconductor device of claim 18, wherein the gate fill material extends along sidewalls of the upper portion of the gate structure.

### Claim 20 (depends on 18)

The semiconductor device of claim 18, wherein sidewalls of the upper portion of the gate structure contact the gate spacers.