# US 11,908,919 B2 · Multi-gate devices with multi-layer inner spacers and fabrication methods thereof

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- Number: US 11,908,919 B2
- Document ID: US11908919B2
- Status: Granted
- Kind: B2
- Application number: 17/200,291
- Filed: 2021-03-12
- Published: 2021-12-02
- Granted: 2024-02-20
- Earliest claimed: 2020-05-28
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chih-Ching Wang; Jon-Hsu Ho; Wen-Hsing Hsieh; Kuan-Lun Cheng; Chung-Wei Wu; Zhiqiang Wu
- Web page: https://patentgrep.com/patent/US11908919B2

## CPC

- H10D 30/023: {having multiple independently-addressable gate electrodes influencing the same channel (manufacture or treatment of dual gate TFTs H10D30/031)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/0195: {forming inner spacers between adjacent channels, e.g. changing their shapes or sizes}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/508: {characterised by the relative sizes, shapes or dispositions of the inner spacers}
- H10D 30/611: {having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733)}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 62/121: {oriented parallel to substrates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method of manufacturing a semiconductor device includes forming a fin structure in which first semiconductor layers and second semiconductor layers are alternatively stacked; forming a sacrificial gate structure over the fin structure; etching a source/drain (S/D) region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming an S/D space; laterally etching the first semiconductor layers through the S/D space, thereby forming recesses; forming a first insulating layer, in the recesses, on the etched first semiconductor layers; after the first insulating layer is formed, forming a second insulating layer, in the recesses, on the first insulating layer, wherein a dielectric constant of the second insulating layer is less than that of the first insulating layer; and forming an S/D epitaxial layer in the S/D space, wherein the second insulating layer is in contact with the S/D epitaxial layer.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, comprising:
forming a fin structure in which first semiconductor layers and second semiconductor layers are alternatingly stacked;
forming a sacrificial gate structure over the fin structure;
etching a source/drain (S/D) region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming an S/D space;
laterally etching the first semiconductor layers through the S/D space, thereby forming recesses;
forming a first insulating layer, in the recesses, on the etched first semiconductor layers;
after the first insulating layer is formed, forming a second insulating layer, in the recesses, on the first insulating layer, wherein a dielectric constant of the second insulating layer is less than that of the first insulating layer; and
after the second insulating layer is formed, forming an S/D epitaxial layer in the S/D space, wherein the second insulating layer is in contact with the S/D epitaxial layer, and wherein the second insulating layer separates the first insulating layer from physically contacting the S/D epitaxial layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first insulating layer has a carbon concentration higher than that of the second insulating layer.

### Claim 3 (depends on 2)

The method of claim 2, wherein the second insulating layer is substantially free of carbon.

### Claim 4 (depends on 1)

The method of claim 1, wherein the second insulating layer has an oxygen concentration higher than that of the first insulating layer.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
after the second insulating layer is formed, forming a third insulating layer, in the recesses, on the second insulating layer.

### Claim 6 (depends on 5)

The method of claim 5, wherein the dielectric constant of the second insulating layer is less than that of the third insulating layer.

### Claim 7 (depends on 5)

The method of claim 5, wherein the first and third insulating layers have a same material composition.

### Claim 8 (depends on 1)

The method of claim 1, wherein the forming of the S/D epitaxial layers results in air gaps formed between the S/D epitaxial layer and the first and second insulating layers.

### Claim 9 (depends on 8)

The method of claim 8, wherein each of the air gaps is defined by the S/D epitaxial layer and the second insulating layer.

### Claim 10 (depends on 1)

The method of claim 1, further comprising:
removing the sacrificial gate structure, thereby exposing the fin structure, removing the first semiconductor layers from the exposed fin structure, thereby forming channel members including the second semiconductor layers; and
forming a gate dielectric layer and a gate electrode layer around the channel members.

### Claim 11

A method of manufacturing a semiconductor device, comprising:
forming a stack of a first type and a second type epitaxial layers on a semiconductor substrate, the first type and second type epitaxial layers having different material compositions and the first type and second type epitaxial layers being alternatingly disposed in a vertical direction;
patterning the stack to form a fin structure;
forming a sacrificial gate structure over the fin structure;
removing at least the first type epitaxial layers from a source/drain (S/D) region of the fin structure, which is not covered by the sacrificial gate structure;
forming a first insulating layer on lateral ends of the first type epitaxial layers, wherein the first insulating layer includes carbon-containing compound;
forming a second insulating layer on the first insulating layer, wherein the second insulating layer includes oxide-containing compound;
after the second insulating layer is formed, forming an S/D epitaxial feature in contact with lateral ends of the second type epitaxial layers;
forming an S/D contact over the S/D epitaxial feature; and
forming a multilayer interconnection over the S/D contact, wherein the first and second insulating layers interpose the S/D epitaxial feature and the first type epitaxial layers, and
wherein the second insulating layer separates the first insulating layer from physically contacting the S/D epitaxial layer.

### Claim 12 (depends on 11)

The method of claim 11, wherein a dielectric constant of the second insulating layer is less than that of the first insulating layer.

### Claim 13 (depends on 11)

The method of claim 11, wherein the first insulating layer includes silicon carbon oxynitride and the second insulating layer includes silicon oxynitride.

### Claim 14 (depends on 11)

The method of claim 11, wherein the S/D epitaxial feature and the second insulating layer jointly define air gaps interposing the S/D epitaxial feature and the first type epitaxial layers.

### Claim 15 (depends on 11)

The method of claim 11, further comprising:
forming a third insulating layer different from the second insulating layer on the second insulating layer, prior to the forming of the epitaxial S/D feature.

### Claim 16 (depends on 15)

The method of claim 15, wherein the second insulating layer separates the third insulating layer from contacting the second type epitaxial layers.

### Claim 17

A method, comprising:
forming a stack of a first type and a second type epitaxial layers on a semiconductor substrate, the first type and second type epitaxial layers having different material compositions and the first type and second type epitaxial layers being alternatingly disposed in a vertical direction;
patterning the stack to form a fin-shape structure;
forming a sacrificial gate structure over the fin-shape structure;
etching the fin-shape structure in a region adjacent to the sacrificial gate structure to form a recess;
laterally etching the first type epitaxial layers from the recess;
depositing a first insulating layer on lateral ends of the first type epitaxial layers;
depositing a second insulating layer on the first insulating layer, wherein material compositions of the first and second insulating layers are different;
depositing a third insulating layer on the second insulating layer, wherein material compositions of the second and third insulating layers are different, and wherein the first and third insulating layers have a same material composition;
forming an epitaxial feature in the recess and in contact with lateral ends of the second type epitaxial layers, wherein the first, second, and third insulating layers interpose the epitaxial feature and the first type epitaxial layers;
completely removing the first type epitaxial layers to release the second type epitaxial layers; and
replacing the sacrificial gate structure with a metal gate structure.

### Claim 18 (depends on 17)

The method of claim 17, wherein each of the first, second, and third insulating layers is in contact with the epitaxial feature.

### Claim 19 (depends on 17)

The method of claim 17, wherein each of the second and third insulating layers is in contact with the epitaxial feature, and the first insulating layer is separated from the epitaxial feature by the second and third insulating layers.

### Claim 20 (depends on 1)

The method of claim 1, wherein the lateral etching of the first semiconductor layers exposes (100) and (110) facets of the first semiconductor layers.