# US 11,908,918 B2 · Electronic device and method of manufacturing the same

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- Number: US 11,908,918 B2
- Document ID: US11908918B2
- Status: Granted
- Kind: B2
- Application number: 18/059,660
- Filed: 2022-11-29
- Published: 2023-04-06
- Granted: 2024-02-20
- Earliest claimed: 2018-09-18
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Jinseong Heo; Yunseong Lee; Sanghyun Jo; Keunwook Shin; Hyeonjin Shin
- Web page: https://patentgrep.com/patent/US11908918B2

## CPC

- H10D 64/033: {comprising ferroelectric layers}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 30/017: {of FETs having two-dimensional material channels, e.g. TMD FETs}
- H10D 30/0314: {of lateral top-gate TFTs comprising only a single gate}
- H10D 30/0415: {of FETs having ferroelectric gate insulators}
- H10D 30/481: {FETs having two-dimensional material channels, e.g. transition metal dichalcogenide [TMD] FETs}
- H10D 30/6739: {Conductor-insulator-semiconductor electrodes}
- H10D 30/675: {Group III-V materials, Group II-VI materials, Group IV-VI materials, selenium or tellurium}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 30/701: {IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs}
- H10D 62/82: Heterojunctions
- H10D 62/882: {Graphene}
- H10D 64/689: {having ferroelectric layers}
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD}
- H10P 14/6544: {to change the morphology of the insulating materials, e.g. transformation of an amorphous layer into a crystalline layer}
- H10P 14/6902: {composed of carbon, e.g. alpha-C, diamond or hydrogen doped carbon}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 14/69391: {the material containing aluminium, e.g. Al2O3}
- H10P 14/69392: {the material containing hafnium, e.g. HfO2}
- H10P 14/69395: {the material containing zirconium, e.g. ZrO2}
- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Provided are electronic devices and methods of manufacturing the same. An electronic device may include a substrate, a gate electrode on the substrate, a ferroelectric layer between the substrate and the gate electrode, and a carbon layer between the substrate and the ferroelectric layer. The carbon layer may have an sp2 bonding structure.

## Claims

### Claim 1

A method of manufacturing an electronic device, the method comprising:
preparing a substrate including a channel element;
depositing a carbon layer on the channel element, the carbon layer having an sp2 bonding structure;
depositing a ferroelectric layer on the carbon layer;
depositing a gate electrode on the ferroelectric layer; and
crystallizing the ferroelectric layer through an annealing process.

### Claim 2 (depends on 1)

The method of claim 1, wherein the preparing the substrate including forming a source and a drain at both sides of the channel element.

### Claim 3 (depends on 1)

The method of claim 1, further comprising:
generating an insulating layer between the substrate and the carbon layer.

### Claim 4 (depends on 1)

The method of claim 1, further comprising:
generating an insulating layer between the carbon layer and the ferroelectric layer.

### Claim 5 (depends on 1)

The method of claim 1, wherein the depositing the carbon layer is performed by chemical vapor deposition (CVD) or atomic layer deposition (ALD).

### Claim 6 (depends on 1)

The method of claim 1, wherein the carbon layer includes nanocrystalline graphene including nano-sized crystals.

### Claim 7 (depends on 1)

The method of claim 1, wherein the depositing the carbon layer includes forming the carbon layer so a thickness of the carbon layer is in a range of 0.4 nm to 100 nm.

### Claim 8 (depends on 1)

The method of claim 1, wherein the depositing the ferroelectric layer is performed by CVD or ALD.