# US 11,908,915 B2 · Method of manufacturing semiconductor devices and semiconductor devices

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- Number: US 11,908,915 B2
- Document ID: US11908915B2
- Status: Granted
- Kind: B2
- Application number: 17/751,328
- Filed: 2022-05-23
- Published: 2022-09-08
- Granted: 2024-02-20
- Earliest claimed: 2020-05-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Shahaji B. More; Chandrashekhar Prakash Savant; Tien-Wei Yu; Chia-Ming Tsai
- Web page: https://patentgrep.com/patent/US11908915B2

## CPC

- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)}
- H10D 64/01338: {with a treatment, e.g. annealing, after the formation of the conductor}
- H10D 64/01342: {by deposition, e.g. evaporation, ALD or laser deposition (H10D64/01344 takes precedence)}
- H10D 64/01344: {in a nitrogen-containing ambient, e.g. N2O oxidation}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/517: {characterised by the conducting layers}
- H10D 64/669: {the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants}
- H10D 84/853: {comprising FinFETs}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 62/121: {oriented parallel to substrates}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0181: {Manufacturing their gate insulating layers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A semiconductor device includes a gate structure disposed over a channel region and a source/drain region. The gate structure includes a gate dielectric layer over the channel region, one or more work function adjustment material layers over the gate dielectric layer, and a metal gate electrode layer over the one or more work function adjustment material layers. The one or more work function adjustment layers includes an aluminum containing layer, and a diffusion barrier layer is disposed at at least one of a bottom portion and a top portion of the aluminum containing layer. The diffusion barrier layer is one or more of a Ti-rich layer, a Ti-doped layer, a Ta-rich layer, a Ta-doped layer and a Si-doped layer.

## Claims

### Claim 1

A gate structure of a semiconductor device, comprising:
a gate dielectric layer disposed over a channel region;
one or more work function adjustment material layers over the gate dielectric layer; and
a metal gate electrode layer disposed over the one or more work function adjustment material layers,
wherein the one or more work function adjustment material layers include a first layer made of WCN and a second layer made of TiAl or TiAlC
a third layer containing Al and Ti is disposed at at least one of a bottom portion or a top portion of the second layer,
the third layer is a Ti-rich layer having a higher Ti concentration than a center of the second layer, and
a Ti concentration in the third layer increases from a side on the center portion to a surface of the second layer.

### Claim 2 (depends on 1)

The gate structure of claim 1, wherein the second layer is made of TiAl.

### Claim 3 (depends on 1)

The gate structure of claim 1, wherein the second layer is disposed over the first layer.

### Claim 4 (depends on 1)

The gate structure of claim 1, wherein the third layer is disposed at the bottom portion of the second layer.

### Claim 5 (depends on 1)

The gate structure of claim 1, wherein the third layer is disposed at the top portion of the second layer.

### Claim 6 (depends on 1)

The gate structure of claim 1, wherein a Ti concentration of the third layer is in a range from 20 atomic % to 50 atomic %.

### Claim 7 (depends on 6)

The gate structure of claim 6, wherein:
a Ti concentration of the center portion of the second layer is in a range from 5 atomic % to 15 atomic %.

### Claim 8 (depends on 1)

The gate structure of claim 1, wherein an aluminum concentration of the second layer is in a range from 10 atomic % to 30 atomic %.

### Claim 9

A semiconductor device, comprising:
a first field effect transistor (FET) including a first gate structure disposed over a first channel region; and
a second FET including a second gate structure disposed over a second channel region, wherein:
the first FET is an n-type FET, and second FET is a p-type FET,
the first gate structure includes:
a first gate dielectric layer;
a first work function adjustment material layer over the first gate dielectric layer;
a second work function adjustment material layer over the first work function adjustment material layer; and
a first metal gate electrode layer over the second work function adjustment material layer,
the second gate structure includes:
a second gate dielectric layer;
a third work function adjustment material layer over the second gate dielectric layer;
a fourth work function adjustment material layer over the third work function adjustment material layer; and
a second metal gate electrode layer over the fourth work function adjustment material layer,
the second and fourth work function adjustment material layers include TiAl or TiAlC, and include a diffusion barrier layer containing Al and Ti at a bottom portion of the second and fourth work function adjustment material layers, respectively,
the diffusion barrier layer is a Ti-rich layer having a higher Ti concentration than a center portion of the second and fourth work function adjustment material layers, and
a Ti concentration in the diffusion barrier layer increases from a side on the center portion to a surface of the second and fourth work function adjustment material layers.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein:
the first work function adjustment material layer and the third work function adjustment material layer are continuously formed between the first FET and the second FET, and
a step is formed at a boundary of the first work function adjustment material layer and the third work function adjustment material layer.

### Claim 11 (depends on 9)

The semiconductor device of claim 9, wherein the first and third work function adjustment material layers include at least one of WN, WCN, or Ru.

### Claim 12 (depends on 9)

The semiconductor device of claim 9, wherein the first gate and the second gate are continuously formed between the first FET and the second FET.

### Claim 13 (depends on 9)

The semiconductor device of claim 9, further comprising a third FET including a third gate structure disposed over a third channel region, wherein:
the third gate structure includes:
a third gate dielectric layer;
a fifth work function adjustment material layer over the third gate dielectric layer;
a sixth work function adjustment material layer over the fifth work function adjustment material layer; and
a third metal gate electrode layer over the sixth work function adjustment material layer,
the fifth work function adjustment material layer is made of a same material as the first work function adjustment material layer,
the sixth work function adjustment material layer is made of a same material as the second work function adjustment material layer, and
a thickness of the third work function adjustment material layer is different from a thickness of the fifth work function adjustment material layer.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein the first gate dielectric layer, the second gate dielectric layer and the third gate dielectric layer are made of different material from each other.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein the first gate dielectric layer, the second gate dielectric layer and the third gate dielectric layer are composed of a high-k dielectric with a different concentration of rare-earth metal.

### Claim 16 (depends on 9)

The semiconductor device of claim 9, further comprising a third FET including a third gate structure disposed over a third channel region, wherein:
the third gate structure includes:
a third gate dielectric layer;
a sixth work function adjustment material layer over the third gate dielectric layer; and
a third metal gate electrode layer over the sixth work function adjustment material layer,
the sixth work function adjustment material layer is made of a same material as the second work function adjustment material layer.

### Claim 17

A method of manufacturing a semiconductor device, comprising:
forming a gate dielectric layer over a channel region made of a semiconductor material;
forming a first work function adjustment layer over the gate dielectric layer; and
forming a metal gate electrode layer over the first work function adjustment layer, wherein:
the first work function adjustment layer includes aluminum and titanium,
the forming the first work function adjustment layer comprises forming a Ti-rich diffusion barrier layer at at least one of a bottom portion and a top portion of the first work function adjustment layer, and
a Ti concentration in the diffusion barrier layer increases from a side on the center portion to a surface of the first work function adjustment material layer.

### Claim 18 (depends on 17)

The method of claim 17, wherein the diffusion barrier layer is formed by gradually changing a source gas for at least one of aluminum and titanium.

### Claim 19 (depends on 17)

The method of claim 17, wherein the first work function adjustment material layer includes TiAl or TiAlC.

### Claim 20 (depends on 17)

The method of claim 17, further comprising a second work function adjustment layer between the first work function adjustment layer and the gate dielectric layer.