# US 11,908,914 B2 · Methods of forming semiconductor structures

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- Number: US 11,908,914 B2
- Document ID: US11908914B2
- Status: Granted
- Kind: B2
- Application number: 17/376,504
- Filed: 2021-07-15
- Published: 2023-01-19
- Granted: 2024-02-20
- Earliest claimed: 2021-07-15
- Assignees: Applied Materials, Inc.
- Applicants: Applied Materials, Inc.
- Inventors: Ria Someshwar; Seshadri Ganguli; Lan Yu; Siddarth Krishnan; Srinivas Gandikota; Jacqueline S. Wrench; Yixiong Yang
- Web page: https://patentgrep.com/patent/US11908914B2

## CPC

- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 30/0212: {using self-aligned silicidation}
- H10D 64/01: Manufacture or treatment
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10W 20/035: {combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers}
- H10W 20/048: {by using plasmas or gaseous environments, e.g. by nitriding}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 84/0193: {the components including FinFETs}
- H10W 20/047: {by introducing additional elements therein}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Methods for forming a semiconductor structure and semiconductor structures are described. The method comprises patterning a substrate to form a first opening and a second opening, the substrate comprising an n transistor and a p transistor, the first opening over the n transistor and the second opening over the p transistor; pre-cleaning the substrate; depositing a titanium silicide (TiSi) layer on the n transistor and on the p transistor by plasma-enhanced chemical vapor deposition (PECVD); optionally depositing a first barrier layer on the titanium silicide (TiSi) layer and selectively removing the first barrier layer from the p transistor; selectively forming a molybdenum silicide (MoSi) layer on the titanium silicide (TiSi) layer on the n transistor and the p transistor; forming a second barrier layer on the molybdenum silicide (MoSi) layer; and annealing the semiconductor structure. The method may be performed in a processing chamber without breaking vacuum.

## Claims

### Claim 1

A method of forming a semiconductor structure, the method comprising:
patterning a substrate to form a first opening and a second opening, the substrate comprising an n transistor and a p transistor, the first opening over the n transistor and the second opening over the p transistor;
pre-cleaning the substrate;
depositing a titanium silicide (TiSi) layer on the n transistor and on the p transistor by plasma-enhanced chemical vapor deposition (PECVD);
optionally depositing a first barrier layer on the titanium silicide (TiSi) layer and selectively removing the first barrier layer from the p transistor;
forming a molybdenum silicide (MoSi) layer on the titanium silicide (TiSi) layer on the n transistor and the p transistor;
forming a second barrier layer on the molybdenum silicide (MoSi) layer; and
annealing the semiconductor structure.

### Claim 2 (depends on 1)

The method of claim 1, wherein the n transistor comprises silicon (Si) doped with phosphorous (P), and the p transistor comprises silicon germanium (SiGe) doped with boron (B).

### Claim 3 (depends on 1)

The method of claim 1, wherein the first barrier layer comprises one or more of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and molybdenum nitride (MoN).

### Claim 4 (depends on 3)

The method of claim 3, wherein the first barrier layer is formed by one or more of an atomic layer deposition (ALD) process or a physical vapor deposition (PVD) process.

### Claim 5 (depends on 1)

The method of claim 1, wherein the second barrier layer comprises molybdenum nitride (MoN), nitridated molybdenum silicide (MoSi) and a PVD metal film.

### Claim 6 (depends on 1)

The method of claim 1, further comprising independently filling the first opening and the second opening with a gapfill material.

### Claim 7 (depends on 6)

The method of claim 6, wherein the gapfill material is substantially free of voids or seams.

### Claim 8 (depends on 6)

The method of claim 6, wherein the gapfill material comprises one or more of tungsten (W), molybdenum (Mo), cobalt (Co) and ruthenium (Ru).

### Claim 9 (depends on 1)

The method of claim 1, wherein annealing the semiconductor structure forms one or more of ohmic and pseudo-ohmic contacts on the n transistor and on the p transistor.

### Claim 10 (depends on 1)

The method of claim 1, wherein the titanium silicide (TiSi) layer on the n transistor has a Schottky barrier height in a range of from about 0.4 eV to about 0.55 eV.

### Claim 11

A method of forming a semiconductor structure, the method comprising:
patterning a substrate to form a first opening, the substrate comprising an n transistor and a p transistor, the first opening over the n transistor;
pre-cleaning the substrate;
depositing a titanium silicide (TiSi) layer on the n transistor by plasma-enhanced chemical vapor deposition (PECVD);
filling the first opening with a first gapfill material;
forming a mask layer on a top surface of the n transistor;
patterning the substrate to form a second opening over the p transistor;
forming a molybdenum silicide (MoSi) layer on the p transistor;
annealing the semiconductor structure; and
filling the second opening with a second gapfill material.

### Claim 12 (depends on 11)

The method of claim 11, wherein the mask layer comprises one or more of a hard mask layer and a photoresist layer.

### Claim 13 (depends on 11)

The method of claim 11, further comprising forming a barrier layer on the titanium silicide (TiSi) layer on the n transistor.

### Claim 14 (depends on 13)

The method of claim 13, further comprising depositing the barrier layer on the molybdenum silicide (MoSi) layer on the p transistor and selectively removing the barrier layer from the p transistor.

### Claim 15 (depends on 13)

The method of claim 13, wherein the barrier layer comprises one or more of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and molybdenum nitride (MoN).

### Claim 16 (depends on 11)

The method of claim 11, wherein the first gapfill material and the second gapfill material independently comprises one or more of tungsten (W), molybdenum (Mo), cobalt (Co) and ruthenium (Ru).