# US 11,908,911 B2 · Thin film transistors with raised source and drain contacts and process for forming such

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- Number: US 11,908,911 B2
- Document ID: US11908911B2
- Status: Granted
- Kind: B2
- Application number: 16/414,481
- Filed: 2019-05-16
- Published: 2020-11-19
- Granted: 2024-02-20
- Earliest claimed: 2019-05-16
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Chieh-Jen Ku; Bernhard Sell; Pei-Hua Wang
- Web page: https://patentgrep.com/patent/US11908911B2

## CPC

- H10D 30/6729: {characterised by the electrodes}
- H10D 64/512: {Disposition of the gate electrodes, e.g. buried gates}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/67: Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)}
- H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A device is disclosed. The device includes a source contact in a source contact trench and a drain contact in a drain contact trench, a channel under the source contact and the drain contact, a first spacing layer on a bottom of the source contact trench and a second spacing layer on a bottom of the drain contact trench. The first spacing layer and the second spacing layer are on the surface of the channel. The device also includes a gate electrode below the channel and a dielectric above the gate electrode and underneath the channel.

## Claims

### Claim 1

A device, comprising:
a source contact in a source contact trench and a drain contact in a drain contact trench;
a channel layer under the source contact and the drain contact, the channel layer having a first depression in a source region beneath the source contact, and the channel layer having a second depression in a drain region beneath the drain contact;
a first spacing layer on a bottom of the source contact and in the first depression in the channel layer, and a second spacing layer on a bottom of the drain contact and in the second depression in the channel layer, wherein the first spacing layer and the second spacing layer are on a surface of the channel layer, each of the first spacing layer and the second spacing layer having a central deeper portion laterally between outer shallower portions, each of the source contact and the drain contact having an upper portion wider than a bottom portion in the respective source contact trench and the drain contact trench;
a gate electrode below the channel layer;
a dielectric above the gate electrode and underneath the channel layer; and
wherein the first spacing layer and the second spacing layer extend a distance of 15 to 30 nm up along sides of the source contact trench and the drain contact trench.

### Claim 2 (depends on 1)

The device of claim 1, wherein a bottom surface of the source contact and a bottom surface of the drain contact is above the first spacing layer and the second spacing layer, respectively, and above the surface of the channel layer.

### Claim 3 (depends on 1)

The device of claim 1, wherein the first spacing layer and the second spacing layer include portions that extend partially up the sides of the source contact trench and partially up the sides of the drain contact trench.

### Claim 4 (depends on 1)

The device of claim 1, wherein the first spacing layer and the second spacing layer include a semiconductor.

### Claim 5 (depends on 1)

The device of claim 1, wherein the first spacing layer and the second spacing layer include an insulator.

### Claim 6 (depends on 1)

The device of claim 1, wherein the first spacing layer and the second spacing layer include oxide.

### Claim 7 (depends on 1)

The device of claim 1, wherein the thickness of the first spacing layer and the thickness of the second spacing layer is 1-5 nm.

### Claim 8 (depends on 1)

The device of claim 1, wherein the source contact and the drain contact include a work function metal.

### Claim 9 (depends on 1)

The device of claim 1, wherein the source contact and the drain contact include a plurality of layers of conductors.

### Claim 10 (depends on 1)

The device of claim 1, wherein the source contact and the drain contact include a single conductor.

### Claim 11

A device, comprising:
a source contact and a drain contact in a source contact trench and a drain contact trench;
a channel layer under the source contact and the drain contact, the channel layer having a first depression in a source region beneath the source contact, and the channel layer having a second depression in a drain region beneath the drain contact;
a first spacing layer on a bottom of the source contact and in the first depression in the channel layer, and a second spacing layer on a bottom of the drain contact and in the second depression in the channel layer, wherein the first spacing layer and the second spacing layer are on a surface of the channel layer and line sidewalls of the source contact trench and the drain contact trench each of the first spacing layer and the second spacing layer having a central deeper portion laterally between outer shallower portions, each of the source contact and the drain contact having an upper portion wider than a bottom portion in the respective source contact trench and the drain contact trench;
a gate electrode below the channel layer; and
a dielectric above the gate electrode and underneath the channel layer; and
wherein the first spacing layer and the second spacing layer extend a distance of 15 to 30 nm up along sides of the source contact trench and the drain contact trench.

### Claim 12 (depends on 11)

The device of claim 11, wherein a bottom surface of the source contact and a bottom surface of the drain contact is above the first spacing layer and the second spacing layer, respectively, and above the surface of the channel layer.

### Claim 13 (depends on 11)

The device of claim 11, wherein the first spacing layer and the second spacing layer is a semiconductor or an insulator.