# US 11,908,910 B2 · Semiconductor device having embedded conductive line and method of fabricating thereof

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- Number: US 11,908,910 B2
- Document ID: US11908910B2
- Status: Granted
- Kind: B2
- Application number: 16/949,363
- Filed: 2020-10-27
- Published: 2022-04-28
- Granted: 2024-02-20
- Earliest claimed: 2020-10-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chih-Chuan Yang; Jing-Yi Lin; Hsin-Wen Su; Shih-Hao Lin
- Web page: https://patentgrep.com/patent/US11908910B2

## CPC

- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10B 10/12: {comprising a MOSFET load element}
- H10B 10/125: {the MOSFET being a thin film transistor [TFT]}
- H10D 30/0245: {by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/834: {comprising FinFETs}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

Methods and devices that provide a first fin structure, a second fin structure, and a third fin structure disposed over a substrate. A dielectric fin is formed between the first fin structure and the second fin structure, and a conductive line is formed between the second fin structure and the third fin structure.

## Claims

### Claim 1

A semiconductor device, comprising:
a first fin structure, a second fin structure, and a third fin structure extending from a substrate;
a first source/drain feature over the first fin structure;
a second source/drain feature over the second fin structure;
a third source/drain feature over the third fin structure;
a dielectric separation structure extending between the first source/drain feature and the second source/drain feature;
a conductive line between the second source/drain feature and the third source/drain feature: and
a metal gate structure over at least two of the first, second and third fin structures, wherein the metal gate structure extends over the conductive line.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising:
a first shallow trench isolation (STI) feature between the first fin structure and the second fin structure; and
a second STI feature extending between the second fin structure and the third fin structure.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the dielectric separation structure is disposed over the first STI feature.

### Claim 4 (depends on 2)

The semiconductor device of claim 2, wherein the conductive line is disposed over the second STI feature.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the first source/drain feature is of a first conductivity type and the second source/drain feature and third source/drain feature are of a second conductivity type.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the conductive line extends parallel each of the first, second and third fin structures.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein the conductive line includes a conductive liner layer.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the conductive liner layer is a silicide composition.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the second fin structure is an active region for a first type of transistor and the third fin structure is an active region for the first type of transistor.

### Claim 10

A semiconductor device, comprising:
a memory cell having a first transistor and a second transistor;
a first source/drain feature of the first transistor formed over a recessed first fin structure, a second source/drain feature of the second transistor formed over a recessed second fin structure; and
a power line disposed between the first source/drain feature and the second source/drain feature:, a dummy region having a first dummy gate and a second dummy gate connected to the first dummy gate; and
another power line disposed between the first dummy gate and the second dummy gate.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the first source/drain feature and the second source/drain feature each include epitaxially grown silicon.

### Claim 12 (depends on 10)

The semiconductor device of claim 10, wherein the first transistor and the second transistor are of a same conductivity type, wherein the same conductivity type is one of n-type or p-type.

### Claim 13 (depends on 10)

The semiconductor device of claim 10, wherein the power line carries Vcc.

### Claim 14 (depends on 10)

The semiconductor device of claim 10, wherein the power line carries Vss.

### Claim 15 (depends on 10)

The semiconductor device of claim 10, further comprising:
a wherein the dummy region having a first dummy gate and the second dummy gate are nonfunctional gates of the semiconductor device connected to the first dummy gate; and
another power line disposed between the first dummy gate and the second dummy gate.

### Claim 16

A method, comprising:
providing a first fin structure, a second fin structure, and a third fin structure disposed over a substrate;
forming a dielectric fin between the first fin structure and the second fin structure;
forming a conductive line between the second fin structure and the third fin structure;
forming a gate structure extending over the second fin structure, the conductive line and the third fin structure;
recessing a source/drain region of each of the first, second and third fin structures; and
epitaxially growing a first, second and third source/drain feature on the first, second, and third fin structures respectively.

### Claim 17 (depends on 16)

The method of claim 16, further comprising:
after the epitaxially growing, removing the gate structure and forming a metal gate structure.

### Claim 18 (depends on 16)

The method of claim 16, wherein the forming the dielectric fin includes:
depositing a first dielectric layer;
depositing a second dielectric layer;
etching back a portion of the second dielectric layer; and
depositing a high-k dielectric layer over the first dielectric layer and second dielectric layer.

### Claim 19 (depends on 16)

The method of claim 16, further comprising:
forming shallow trench isolation (STI) features between the first fin structure and the second fin structure and between the second fin structure and the third fin structure, wherein the dielectric fin is formed over one of the STI features and the conductive line is formed over another of the STI features.

### Claim 20 (depends on 16)

The method of claim 16, further comprising:
after forming the gate structure, forming a silicide layer between the conductive line and the epitaxially grown second source/drain feature.