# US 11,908,906 B2 · Semiconductor structure and fabrication method thereof

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- Number: US 11,908,906 B2
- Document ID: US11908906B2
- Status: Granted
- Kind: B2
- Application number: 17/446,017
- Filed: 2021-08-26
- Published: 2022-03-10
- Granted: 2024-02-20
- Earliest claimed: 2020-09-07
- Assignees: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Applicants: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Inventors: Hailong Yu; Xuezhen Jing; Hao Zhang; Tiantian Zhang; Jinhui Meng
- Web page: https://patentgrep.com/patent/US11908906B2

## CPC

- H10D 64/251: {Source or drain electrodes for field-effect devices}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/42: Vias, e.g. via plugs
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure and a fabrication method of the semiconductor structure are provided. The method includes providing a substrate, forming a first dielectric layer and a plurality of gate structures, forming source-drain doped regions, and forming a source-drain plug. The first dielectric layer covers surfaces of the gate structure, the source-drain doped region and the source-drain plug. The method also includes forming a first plug in the first dielectric layer, and forming a second dielectric layer on the first dielectric layer. The first plug is in contact with a top surface of one of the source-drain plug and the gate structure. The second dielectric layer covers the first plug. Further, the method includes forming a second plug material film in the first and second dielectric layers. The second plug material film is in contact with the top surface of one of the source-drain plug and the gate structure.

## Claims

### Claim 1

A fabrication method of a semiconductor structure, comprising:
providing a substrate;
forming a first dielectric layer and a plurality of gate structures over the substrate, forming source-drain doped regions in the substrate on both sides of a gate structure of the plurality of gate structures, and forming a source-drain plug on a top surface of a source-drain doped region of the source-drain doped regions, wherein the first dielectric layer covers surfaces of the gate structure, the source-drain doped region and the source-drain plug;
forming a first plug in the first dielectric layer, wherein the first plug is in contact with one of a top surface of the source-drain plug and a top surface of the gate structure;
forming a second dielectric layer on a surface of the first dielectric layer, wherein the second dielectric layer covers a surface of the first plug;
forming a second plug material film in the first dielectric layer and the second dielectric layer, wherein the second plug material film is in contact with one of the top surface of the source-drain plug and the top surface of the gate structure; and
planarizing the second plug material film until the surface of the first dielectric layer and a top surface of the first plug are exposed, to form a second plug in the first dielectric layer, wherein the second plug is in contact with one of the top surface of the source-drain plug and the top surface of the gate structure.

### Claim 2 (depends on 1)

The method according to claim 1, wherein forming the first plug includes:
forming a first opening in the first dielectric layer, wherein the first opening exposes one of the top surface of the source-drain plug and the top surface of the gate structure;
forming a first plug material film in the first opening and on the surface of the first dielectric layer; and
planarizing the first plug material film until the surface of the first dielectric layer is exposed, to form the first plug in the first opening.

### Claim 3 (depends on 2)

The method according to claim 2, wherein forming the first opening includes:
forming a first patterned layer on the surface of the first dielectric layer, wherein the first patterned layer exposes a portion of the first dielectric layer; and
using the first patterned layer as a mask, etching the first dielectric layer until one of the top surface of the source-drain plug and the top surface of the gate structure is exposed, to form the first opening.

### Claim 4 (depends on 2)

The method according to claim 2, wherein forming the first plug material film includes:
a selective metal growth process, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process.

### Claim 5 (depends on 4)

The method according to claim 4, wherein:
when the first opening exposes the top surface of the source-drain plug, the first plug material film is formed by the selective metal growth process; and
parameters of the selective metal growth process include:
gases including WF6 and H2, wherein a flow rate of WF6 is in a range of approximately 20 sccm-150 sccm, and a flow rate of H2 is in a range of approximately 5000 sccm-8000 sccm, and
a temperature in a range of approximately 200° C.-400° C.

### Claim 6 (depends on 1)

The method according to claim 1, wherein:
the first plug is made of a material including one or more of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride, and aluminum.

### Claim 7 (depends on 1)

The method according to claim 1, wherein:
the second plug material film is made of a material including one or more of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride, and aluminum.

### Claim 8 (depends on 1)

The method according to claim 1, wherein:
the second plug material film is further formed on a surface of the second dielectric layer; and
forming the second plug material film includes:
forming a second opening in the first dielectric layer and the second dielectric layer, wherein the second opening exposes one of the top surface of the source-drain plug and the top surface of the gate structure, and
forming the second plug material film in the second opening and on the surface of the second dielectric layer.

### Claim 9 (depends on 8)

The method according to claim 8, wherein forming the second opening includes:
forming a second patterned layer on the surface of the second dielectric layer, wherein the second patterned layer exposes a portion of the second dielectric layer; and
using the second patterned layer as a mask, etching the first dielectric layer and the second dielectric layer until one of the top surface of the source-drain plug and the top surface of the gate structure is exposed, to form the second opening.

### Claim 10 (depends on 1)

The method according to claim 1, wherein:
the second plug material film is formed by a selective metal growth process; and
parameters of the selective metal growth process include:
gases including WF6 and H2, wherein a flow rate of WF6 is in a range of approximately 20 sccm-150 sccm, and a flow rate of H2 is in a range of approximately 5000 sccm-8000 sccm, and
a temperature in a range of approximately 200° C.-400° C.

### Claim 11 (depends on 1)

The method according to claim 1, wherein:
the first plug is in contact with the top surface of the gate structure, and the second plug material film is in contact with the top surface of the source-drain plug.

### Claim 12 (depends on 1)

The method according to claim 1, wherein:
the first plug is in contact with the top surface of the source-drain plug, and the second plug material film is in contact with the top surface of the gate structure.

### Claim 13 (depends on 1)

The method according to claim 1, wherein:
the first dielectric layer is made of a dielectric material including one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxy-carbide, silicon oxy-nitride, aluminum oxide, aluminum nitride, silicon carbo-nitride, and silicon oxy-carbo-nitride.

### Claim 14 (depends on 1)

The method according to claim 1, wherein:
the second dielectric layer is made of a dielectric material including one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxy-carbide, silicon oxy-nitride, aluminum oxide, aluminum nitride, silicon carbo-nitride, and silicon oxy-carbo-nitride.

### Claim 15 (depends on 1)

The method according to claim 1, wherein:
the source-drain plug includes an isolation layer and a conductive layer on the isolation layer, wherein:
the isolation layer is made of a material including one or more of titanium silicide, tantalum silicide, and tungsten nitride, and
the conductive layer is made of a material including one or more of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride, and aluminum.

### Claim 16 (depends on 1)

The method according to claim 1, wherein:
the gate structure includes a gate dielectric layer, a work function layer on the gate dielectric layer, and a gate electrode layer on the work function layer, wherein:
the gate dielectric layer is made of a material including one or more of silicon oxide, and a high-K dielectric material,
the work function layer is made of a material including one or more of TiN, TaN, TiAl, TiAlC, TaAlN, TiAlN, TaCN, and AlN, and
the gate electrode layer is made of a material including one or more of tungsten, copper, cobalt, titanium nitride, titanium, tantalum, tantalum nitride, ruthenium, ruthenium nitride, and aluminum.

### Claim 17

A semiconductor structure, comprising:
a first dielectric layer and a plurality of gate structures disposed over a substrate, source-drain doped regions disposed in the substrate on both sides of a gate structure of the plurality of gate structures, and a source-drain plug disposed on a top surface of a source-drain doped region of the source-drain doped regions, wherein the first dielectric layer covers surfaces of the gate structure, the source-drain doped region and the source-drain plug;
a first plug disposed in the first dielectric layer, wherein the first plug is in contact with one of a top surface of the source-drain plug and a top surface of the gate structure;
a second dielectric layer disposed on the first dielectric layer, wherein the second dielectric layer covers a surface of the first plug; and
a second plug material film disposed in the first dielectric layer and the second dielectric layer, wherein the second plug material film is in contact with one of the top surface of the source-drain plug and the top surface of the gate structure.

### Claim 18 (depends on 17)

The semiconductor structure according to claim 17, wherein:
the first plug is in contact with the top surface of the gate structure, and the second plug material film is in contact with the top surface of the source-drain plug.

### Claim 19 (depends on 17)

The semiconductor structure according to claim 17, wherein:
the first plug is in contact with the top surface of the source-drain plug, and the second plug material film is in contact with the top surface of the gate structure.