# US 11,908,905 B2 · Electrode structure for vertical group III-V device

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- Number: US 11,908,905 B2
- Document ID: US11908905B2
- Status: Granted
- Kind: B2
- Application number: 17/867,012
- Filed: 2022-07-18
- Published: 2022-11-03
- Granted: 2024-02-20
- Earliest claimed: 2020-05-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Yao-Chung Chang; Chun Lin Tsai; Ru-Yi Su; Wei Wang; Wei-Chen Yang
- Web page: https://patentgrep.com/patent/US11908905B2

## CPC

- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 64/23: Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
- H10D 8/01: Manufacture or treatment
- H10D 8/422: {PN diodes having the PN junctions in mesas}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 62/159: {Shapes}
- H10D 64/252: {for vertical or pseudo-vertical devices}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 8/50: PIN diodes
- H10D 30/477: {Vertical HEMTs or vertical HHMTs}
- H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure, the method includes forming a buffer layer over a substrate. An active layer is formed on the buffer layer. A top electrode is formed on the active layer. An etch process is performed on the buffer layer and the substrate to define a plurality of pillar structures. The plurality of pillar structures include a first pillar structure laterally offset from a second pillar structure. At least portions of the first and second pillar structures are spaced laterally between sidewalls of the top electrode.

## Claims

### Claim 1

A method for forming a semiconductor structure, comprising:
forming a buffer layer over a substrate;
forming an active layer on the buffer layer;
forming a top electrode on the active layer; and
performing an etch process on the buffer layer and the substrate to define a plurality of pillar structures, wherein the plurality of pillar structures comprise a first pillar structure laterally offset from a second pillar structure, wherein at least portions of the first and second pillar structures are spaced laterally between sidewalls of the top electrode, wherein the etch process is performed while the top electrode is disposed on the active layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein a height of the first pillar structure is greater than a width of the first pillar structure.

### Claim 3 (depends on 1)

The method of claim 1, further comprising:
doping the active layer to form a first doped region and a second doped region within the active layer, wherein the first doped region overlies the second doped region.

### Claim 4 (depends on 3)

The method of claim 3, wherein the first and second doped regions are formed before the etch process.

### Claim 5 (depends on 3)

The method of claim 3, wherein the etch process removes at least a portion of the second doped region.

### Claim 6 (depends on 1)

The method of claim 1, wherein a width of the top electrode is greater than a sum of a width of the first pillar structure and a width of the second pillar structure.

### Claim 7 (depends on 1)

The method of claim 1, further comprising:
forming a bottom electrode along the plurality of pillar structures, wherein the bottom electrode comprises elongated vertical conductive segments disposed between adjacent pillar structures in the plurality of pillar structures.

### Claim 8

A method for forming a semiconductor structure, comprising:
forming a stack of group III-V layers over a substrate;
performing an etch process on the stack of group III-V layers to define a plurality of elongated vertical segments defined by sidewalls of the stack of group III-V layers and sidewalls of the substrate; and
forming a bottom electrode on the substrate and the stack of group III-V layers, wherein the bottom electrode comprises a plurality of conductive segments disposed between adjacent elongated vertical segments and a conductive body disposed on the elongated vertical segments between adjacent conductive segments, wherein a width of the conductive body between the adjacent conductive segments is less than a height of the plurality of conductive segments.

### Claim 9 (depends on 8)

The method of claim 8, wherein the stack of group III-V layers is formed by one or more epitaxial growth processes.

### Claim 10 (depends on 8)

The method of claim 8, further comprising:
forming an isolation structure within the stack of group III-V layers, wherein the conductive segments are disposed between sidewalls of the isolation structure.

### Claim 11 (depends on 8)

The method of claim 8, wherein the etch process defines a plurality of openings in the stack of group III-V layers, wherein the openings have a first shape when viewed in cross section and a second shape when viewed from a top view, wherein the first shape is different from the second shape.

### Claim 12 (depends on 8)

The method of claim 8, further comprising:
forming a top electrode over the stack of group III-V layers, wherein a width of the top electrode is greater than the width of the conductive body between the adjacent conductive segments.

### Claim 13 (depends on 12)

The method of claim 12, wherein a thickness of the top electrode is greater than a thickness of the bottom electrode.

### Claim 14 (depends on 8)

The method of claim 8, further comprising:
performing a doping process on the stack of group III-V layers before performing the etch process to form one or more doped regions in the stack of group III-V layers.

### Claim 15 (depends on 8)

The method of claim 8, further comprising:
forming an interconnect structure on the stack of group III-V layers, wherein the interconnect structure comprises a plurality of conductive vias and a plurality of conductive wires.

### Claim 16

A method for forming a semiconductor device, the method comprising:
forming a buffer layer over a substrate, wherein the buffer layer comprises a first group III-V material;
forming an active layer over the buffer layer, wherein the active layer comprises a second group III-V material different than the first group III-V material;
forming a top electrode along a first surface of the active layer;
performing a patterning process on the buffer layer and the substrate to define a plurality of openings and a plurality of pillar structures, such that the pillar structures are laterally offset from one another by a respective opening in the plurality of openings, wherein the patterning process exposes a second surface of the active layer, wherein the second surface is opposite the first surface, wherein widths of the openings are respectively greater than widths of the pillar structures; and
forming a bottom electrode along the substrate, the buffer layer, and the active layer, wherein the bottom electrode directly contacts the second surface of the active layer, wherein the bottom electrode laterally surrounds each pillar structure in the plurality of pillar structures.

### Claim 17 (depends on 16)

The method of claim 16, wherein forming the buffer layer includes performing a metal organic chemical vapor deposition (MOCVD) process, wherein forming the active layer includes performing a molecular beam epitaxy (MBE) process.

### Claim 18 (depends on 16)

The method of claim 16, wherein the patterning process removes at least a portion of the active layer.

### Claim 19 (depends on 16)

The method of claim 16, wherein a lattice constant of the active layer conforms to a lattice constant of the buffer layer.

### Claim 20 (depends on 16)

The method of claim 16, further comprising:
performing an etching process on the active layer to form isolation regions in the active layer, wherein the etching process is performed before the patterning process.