# US 11,908,904 B2 · Planar gate semiconductor device with oxygen-doped Si-layers > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,908,904 B2 - Document ID: US11908904B2 - Status: Granted - Kind: B2 - Application number: 17/400,575 - Filed: 2021-08-12 - Published: 2023-02-16 - Granted: 2024-02-20 - Earliest claimed: 2021-08-12 - Assignees: Infineon Technologies Austria AG - Applicants: Infineon Technologies Austria AG - Inventors: Sylvain Leomant; Thomas Feil; Yulia Polak; Maximilian Roesch - Web page: https://patentgrep.com/patent/US11908904B2 ## CPC - H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates} - H10D 30/66: Vertical DMOS [VDMOS] FETs - H10D 62/156: {Drain regions of DMOS transistors} - H10D 62/8161: {potential variation due to variations in composition or crystallinity, e.g. heterojunction superlattices (lateral superlattices, lateral surface superlattices H10D62/8181)} - H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)} - H10D 84/83: of only insulated-gate FETs [IGFET] - H10D 12/461: {having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions} - H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)} - H10D 62/60: Impurity distributions or concentrations - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor device includes: a semiconductor substrate having opposing first and second main surfaces; a plurality of transistor cells each including a source region, a drift zone, a body region separating the source region from the drift zone, a field plate trench extending into the drift zone and including a field plate, and a planar gate on the first main surface and configured to control current through a channel of the body region; a drain region at the second main surface; and a diffusion barrier structure including alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si. The diffusion barrier structure may be interposed between body regions of adjacent transistor cells and/or extend along the channel of each transistor cell and/or vertically extend in the semiconductor substrate between adjacent field plate trenches. ## Claims ### Claim 1 A semiconductor device, comprising: a semiconductor substrate having a first main surface and a second main surface opposite the first main surface; a plurality of transistor cells, each transistor cell comprising a source region of a first conductivity type, a drift zone of the first conductivity type, a body region of a second conductivity type separating the source region from the drift zone, a field plate trench extending into the drift zone and including a field plate, and a planar gate on the first main surface and configured to control current through a channel of the body region; a drain region of the first conductivity type at the second main surface; and a diffusion barrier structure interposed between body regions of adjacent transistor cells, the diffusion barrier structure comprising alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the diffusion barrier structure extends into the body region of each transistor cell along the channel of the body region. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein the diffusion barrier structure vertically extends in the semiconductor substrate between adjacent field plate trenches. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein the semiconductor substrate includes a plurality of epitaxial layers with different vertical doping profiles between the drain region and the field plate trenches, and wherein the diffusion barrier structure delimits the different vertical doping profiles. ### Claim 5 (depends on 1) The semiconductor device of claim 1, wherein the diffusion barrier structure extends along the drain region. ### Claim 6 (depends on 1) The semiconductor device of claim 1, wherein the source region and the body region of each transistor cell are vertically aligned with a respective field plate trench, and wherein the diffusion barrier structure laterally extends from the source region to the drift zone along the channel of the body region. ### Claim 7 (depends on 6) The semiconductor device of claim 6, wherein the diffusion barrier structure vertically extends in the semiconductor substrate between adjacent field plate trenches in a direction toward the drain region. ### Claim 8 (depends on 1) The semiconductor device of claim 1, wherein the source region and the body region of each transistor cell are vertically aligned with a semiconductor mesa delimited by adjacent field plate trenches, and wherein the diffusion barrier structure extends along the channel of the body region and into the semiconductor mesa delimited by the respective adjacent field plate trenches. ### Claim 9 A semiconductor device, comprising: a semiconductor substrate having a first main surface and a second main surface opposite the first main surface; a plurality of transistor cells, each transistor cell comprising a source region of a first conductivity type, a drift zone of the first conductivity type, a body region of a second conductivity type separating the source region from the drift zone, a field plate trench extending into the drift zone and including a field plate, and a planar gate on the first main surface and configured to control current through a channel of the body region; a drain region of the first conductivity type at the second main surface; and a diffusion barrier structure extending along the channel of the body region, the diffusion barrier structure comprising alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si. ### Claim 10 (depends on 9) The semiconductor device of claim 9, wherein the diffusion barrier structure vertically extends in the semiconductor substrate between adjacent field plate trenches. ### Claim 11 (depends on 9) The semiconductor device of claim 9, wherein the semiconductor substrate includes a plurality of epitaxial layers with different vertical doping profiles between the drain region and the field plate trenches of the transistor cells, and wherein the diffusion barrier structure delimits the different vertical doping profiles. ### Claim 12 (depends on 9) The semiconductor device of claim 9, wherein the diffusion barrier structure extends along the drain region. ### Claim 13 (depends on 9) The semiconductor device of claim 9, wherein the source region and the body region of each transistor cell are vertically aligned with a respective field plate trench, and wherein the diffusion barrier structure laterally extends from the source region to the drift zone along the channel of the body region. ### Claim 14 (depends on 13) The semiconductor device of claim 13, wherein the diffusion barrier structure vertically extends in the semiconductor substrate between adjacent field plate trenches in a direction toward the drain region. ### Claim 15 (depends on 9) The semiconductor device of claim 9, wherein the source region and the body region of each transistor cell are vertically aligned with a semiconductor mesa delimited by adjacent field plate trenches, and wherein the diffusion barrier structure extends along the channel of the body region and into the semiconductor mesa delimited by the respective adjacent field plate trenches. ### Claim 16 A semiconductor device, comprising: a semiconductor substrate having a first main surface and a second main surface opposite the first main surface; a plurality of transistor cells, each transistor cell comprising a source region of a first conductivity type, a drift zone of the first conductivity type, a body region of a second conductivity type separating the source region from the drift zone, a field plate trench extending into the drift zone and including a field plate, and a planar gate on the first main surface and configured to control current through a channel of the body region; a drain region of the first conductivity type at the second main surface; and a diffusion barrier structure vertically extending in the semiconductor substrate from the body region of the plurality of transistor cells and into the drift zone between adjacent field plate trenches, the diffusion barrier structure comprising alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si. ### Claim 17 (depends on 16) The semiconductor device of claim 16, wherein the diffusion barrier structure extends into the body region of each transistor cell along the channel of the body region. ### Claim 18 (depends on 16) The semiconductor device of claim 16, wherein the semiconductor substrate includes a plurality of epitaxial layers with different vertical doping profiles between the drain region and the field plate trenches of the transistor cells, and wherein the diffusion barrier structure delimits the different vertical doping profiles. ### Claim 19 (depends on 16) The semiconductor device of claim 16, wherein the diffusion barrier structure extends along the drain region. ### Claim 20 (depends on 16) The semiconductor device of claim 16, wherein the source region and the body region of each transistor cell are vertically aligned with a respective field plate trench, and wherein the diffusion barrier structure laterally extends from the source region to the drift zone along the channel of the body region. ### Claim 21 (depends on 20) The semiconductor device of claim 20, wherein the diffusion barrier structure vertically extends in the semiconductor substrate between adjacent field plate trenches in a direction toward the drain region. ### Claim 22 (depends on 16) The semiconductor device of claim 16, wherein the source region and the body region of each transistor cell are vertically aligned with a semiconductor mesa delimited by adjacent field plate trenches, and wherein the diffusion barrier structure extends along the channel of the body region and into the semiconductor mesa delimited by the respective adjacent field plate trenches.