# US 11,908,903 B2 · Process window control for gate formation in semiconductor devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,908,903 B2 - Document ID: US11908903B2 - Status: Granted - Kind: B2 - Application number: 17/370,750 - Filed: 2021-07-08 - Published: 2023-01-12 - Granted: 2024-02-20 - Earliest claimed: 2021-07-08 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company Limited - Inventors: Kuei-Yu Kao; Shih-Yao Lin; Chen-Ping Chen; Chih-Han Lin; Ming-Ching Chang; Chao-Cheng Chen - Web page: https://patentgrep.com/patent/US11908903B2 ## CPC - H10D 64/01: Manufacture or treatment - H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels} - H10D 30/023: {having multiple independently-addressable gate electrodes influencing the same channel (manufacture or treatment of dual gate TFTs H10D30/031)} - H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels} - H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around} - H10D 62/118: {Nanostructure semiconductor bodies} - H10D 62/121: {oriented parallel to substrates} - H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels} - B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic - H10D 84/0151: {Manufacturing their isolation regions} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES ## Abstract A method of fabricating a semiconductor structure includes selective use of a cladding layer during the fabrication process to provide critical dimension uniformity. The cladding layer can be formed before forming a recess in an active channel structure or can be formed after filling a recess in an active channel structure with dielectric material. These techniques can be used in semiconductor structures such as gate-all-around (GAA) transistor structures implemented in an integrated circuit. ## Claims ### Claim 1 A method of fabricating a semiconductor structure, comprising: removing a portion of an active channel structure to form a recess; filling the recess with dielectric material; forming a cladding layer adjacent the active channel structure but not adjacent the dielectric material; forming a gate structure around the active channel structure, wherein the gate structure comprises an active gate structure; forming a dummy gate structure around the active channel structure; and removing the dummy gate structure before forming the active gate structure. ### Claim 2 (depends on 1) The method of claim 1, wherein forming the cladding layer comprises forming a layer of silicon germanium adjacent the active channel structure but not adjacent the dielectric material. ### Claim 3 (depends on 1) The method of claim 1, wherein forming the cladding layer comprises forming the cladding layer using an epitaxial growth process. ### Claim 4 (depends on 1) The method of claim 1, wherein the gate structure comprises a first gate structure, the method further comprising forming a second gate structure around the active channel structure such that a width of the first gate structure is equal to a width of the second gate structure. ### Claim 5 (depends on 1) The method of claim 1, further comprising forming an epitaxial region around the active channel structure. ### Claim 6 (depends on 1) The method of claim 1, further comprising removing a portion of an isolation structure adjacent the active channel structure before forming the cladding layer adjacent the active channel structure. ### Claim 7 (depends on 1) The method of claim 1, wherein forming the cladding layer comprises forming a layer of silicon germanium adjacent the active channel structure. ### Claim 8 A method of fabricating a semiconductor structure, comprising: forming a cladding layer adjacent a first side, a second side, a third side, and a fourth side of an active channel structure; forming a recess by removing a portion of the cladding layer and a portion of the active channel structure such that after forming the recess the cladding layer is adjacent the first side, the second side, and the third side of the active channel structure, but not adjacent the fourth side of the active channel structure; filling the recess with dielectric material; and forming a gate structure around the active channel structure, wherein forming the cladding layer comprises forming a layer of silicon germanium adjacent the first side, the second side, the third side, and the fourth side of the active channel structure. ### Claim 9 (depends on 8) The method of claim 8, further comprising forming an epitaxial region around the active channel structure. ### Claim 10 (depends on 8) The method of claim 8, wherein the gate structure comprises an active gate structure, the method further comprising: forming a dummy gate structure around the active channel structure; and removing the dummy gate structure before forming the active gate structure. ### Claim 11 (depends on 8) The method of claim 8, wherein the gate structure comprises a first gate structure, the method further comprising forming a second gate structure around the active channel structure such that a width of the first gate structure is equal to a width of the second gate structure. ### Claim 12 (depends on 11) The method of claim 11, wherein filling the recess with dielectric material comprises filling the recess with dielectric material such that a width of the dielectric material is greater than the width of the first gate structure and the width of the second gate structure. ### Claim 13 (depends on 8) The method of claim 8, wherein forming the cladding layer comprises forming the cladding layer using an epitaxial growth process. ### Claim 14 (depends on 8) The method of claim 8, wherein forming the cladding layer comprises forming a layer of silicon germanium adjacent the active channel structure. ### Claim 15 A method of fabricating a semiconductor structure, comprising: forming a cladding layer around an active channel structure; removing a portion of the cladding layer and a portion of the active channel structure after forming the cladding layer around the active channel structure; forming a gate structure around the active channel structure, wherein the gate structure comprises an active gate structure; forming a dummy gate structure around the active channel structure; and removing the dummy gate structure before forming the active gate structure. ### Claim 16 (depends on 15) The method of claim 15, wherein forming the cladding layer comprises growing the cladding layer around the active channel structure using an epitaxial growth process. ### Claim 17 (depends on 15) The method of claim 15, wherein removing the portion of the cladding layer and the portion of the active channel structure comprises removing the portion of the cladding layer and the portion of the active channel structure to form a recess, the method further comprising forming dielectric material within the recess. ### Claim 18 (depends on 15) The method of claim 15, further comprising forming an epitaxial region around the active channel structure. ### Claim 19 (depends on 15) The method of claim 15, wherein the gate structure comprises a first gate structure, the method further comprising forming a second gate structure around the active channel structure such that a width of the first gate structure is equal to a width of the second gate structure. ### Claim 20 (depends on 15) The method of claim 15, wherein forming the cladding layer comprises forming a layer of silicon germanium adjacent the active channel structure.