# US 11,908,900 B2 · Passivation layer for epitaxial semiconductor process > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,908,900 B2 - Document ID: US11908900B2 - Status: Granted - Kind: B2 - Application number: 17/869,885 - Filed: 2022-07-21 - Published: 2022-11-17 - Granted: 2024-02-20 - Earliest claimed: 2020-05-28 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Yin-Kai Liao; Sin-Yi Jiang; Hsiang-Lin Chen; Yi-Shin Chu; Po-Chun Liu; Kuan-Chieh Huang; Jyh-Ming Hung; Jen-Cheng Liu - Web page: https://patentgrep.com/patent/US11908900B2 ## CPC - H10D 62/378: {Contact regions to the substrate regions} - H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET} - H10D 62/834: further characterised by the dopants - H10D 64/663: {the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract The present disclosure relates to an integrated chip. The integrated chip includes a substrate having a first semiconductor material. A second semiconductor material is disposed on the first semiconductor material. The second semiconductor material is a group IV semiconductor or a group III-V compound semiconductor. A passivation layer is disposed on the second semiconductor material. The passivation layer includes the first semiconductor material. A first doped region and a second doped region extend through the passivation layer and into the second semiconductor material. ## Claims ### Claim 1 An integrated chip, comprising: a substrate comprising a first semiconductor material; a second semiconductor material disposed on the first semiconductor material, wherein the second semiconductor material is a group IV semiconductor or a group III-V compound semiconductor; a passivation layer disposed on the second semiconductor material, wherein the passivation layer comprises the first semiconductor material; and a first doped region and a second doped region extending through the passivation layer and into the second semiconductor material, wherein the first doped region has a first doping type and the second doped region has a second doping type that is different than the first doping type. ### Claim 2 (depends on 1) The integrated chip of claim 1, wherein the first semiconductor material is silicon. ### Claim 3 (depends on 1) The integrated chip of claim 1, wherein the first semiconductor material of the substrate vertically and laterally contacts the second semiconductor material. ### Claim 4 (depends on 1) The integrated chip of claim 1, wherein the passivation layer contacts a topmost surface of the second semiconductor material. ### Claim 5 (depends on 1) The integrated chip of claim 1, further comprising: a silicide arranged within the passivation layer and along tops of the first doped region and the second doped region. ### Claim 6 (depends on 1) The integrated chip of claim 1, wherein the first semiconductor material is silicon and the second semiconductor material is germanium. ### Claim 7 (depends on 1) The integrated chip of claim 1, wherein the substrate has sidewalls and a horizontally extending surface that define a recess within the substrate; and wherein the second semiconductor material is arranged within the recess. ### Claim 8 (depends on 7) The integrated chip of claim 7, wherein the second semiconductor material has angled sidewalls that cause the second semiconductor material to have a first width that increases as a first distance over the horizontally extending surface increases; and wherein the passivation layer has angled sidewalls that cause the passivation layer to have a second width that decreases as a second distance over the horizontally extending surface increases. ### Claim 9 (depends on 1) The integrated chip of claim 1, wherein the first doped region and the second doped region are vertically separated from a bottom of the second semiconductor material by one or more non-zero distances. ### Claim 10 An integrated chip, comprising: a substrate comprising silicon, the substrate having interior sidewalls and a recessed upper surface that form a recess within an upper surface of the substrate; a second semiconductor material arranged along the interior sidewalls and the recessed upper surface of the substrate, wherein the second semiconductor material comprises a group IV semiconductor or a group III-V compound semiconductor; a passivation layer comprising silicon, wherein the silicon of the passivation layer contacts an uppermost surface of the second semiconductor material; a first doped region having a first doping type and extending through the passivation layer and into the second semiconductor material; and a second doped region having a second doping type and extending through the passivation layer and into the second semiconductor material, wherein the first doped region and the second doped region are separated from a bottommost surface of the second semiconductor material by the second semiconductor material. ### Claim 11 (depends on 10) The integrated chip of claim 10, further comprising: a plurality of interconnects disposed within an inter-level dielectric (ILD) structure over the substrate, wherein the ILD structure extends along sidewalls of the passivation layer. ### Claim 12 (depends on 10) The integrated chip of claim 10, wherein the first doped region and the second doped region define a photonic device. ### Claim 13 (depends on 10) The integrated chip of claim 10, wherein the second semiconductor material has a different width than the passivation layer. ### Claim 14 (depends on 10) The integrated chip of claim 10, wherein the passivation layer has sidewalls directly over the substrate. ### Claim 15 (depends on 10) The integrated chip of claim 10, wherein the second semiconductor material continuously extends between the bottommost surface, which contacts the silicon of the substrate, and a topmost surface contacting the silicon of the passivation layer. ### Claim 16 (depends on 10) The integrated chip of claim 10, wherein the substrate has a first upper surface directly below the passivation layer and a second upper surface laterally outside of the passivation layer, the second upper surface being recessed below the first upper surface. ### Claim 17 (depends on 10) The integrated chip of claim 10, wherein the first doped region and the second doped region are laterally separated from an interface between sidewalls of the substrate and the second semiconductor material. ### Claim 18 (depends on 10) The integrated chip of claim 10, wherein the second semiconductor material is below the upper surface of the substrate. ### Claim 19 An integrated chip, comprising: a substrate comprising a first semiconductor material; a second semiconductor material disposed on the substrate, wherein the first semiconductor material is a different semiconductor material than the second semiconductor material; a passivation layer disposed on the second semiconductor material; a first doped region having a first doping type, the first doped region extending through the passivation layer and into the second semiconductor material, wherein the first doped region has a top that is vertically above a top of the second semiconductor material and a bottom that is vertically above a bottom of the second semiconductor material; and a second doped region having a second doping type, the second doped region extending through the passivation layer and into the second semiconductor material. ### Claim 20 (depends on 19) The integrated chip of claim 19, wherein the first doping type and the second doping type are different doping types.