# US 11,908,899 B2 · MOSFET and memory cell having improved drain current through back bias application

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- Number: US 11,908,899 B2
- Document ID: US11908899B2
- Status: Granted
- Kind: B2
- Application number: 17/535,473
- Filed: 2021-11-24
- Published: 2022-03-17
- Granted: 2024-02-20
- Earliest claimed: 2009-02-20
- Assignees: Zeno Semiconductor, Inc.
- Applicants: Zeno Semiconductor, Inc.
- Inventors: Jin-Woo Han; Yuniarto Widjaja; Zvi Or-Bach; Dinesh Maheshwari
- Web page: https://patentgrep.com/patent/US11908899B2

## CPC

- H10D 62/378: {Contact regions to the substrate regions}
- G11C 11/404: with one charge-transfer gate, e.g. MOS transistor, per cell
- G11C 16/04: using variable threshold transistors, e.g. FAMOS
- G11C 16/0416: {comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM}
- G11C 16/10: Programming or data input circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6733: {Multi-gate TFTs}
- H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs}
- H10D 30/6758: {characterised by the insulating substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/512: {Disposition of the gate electrodes, e.g. buried gates}
- H10D 84/0191: {Manufacturing their doped wells}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/837: {comprising vertical IGFETs}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/853: {comprising FinFETs}
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10D 86/215: {comprising FinFETs}
- H10D 89/213: {in field-effect devices}
- H10W 10/031: {of isolation regions comprising PN junctions}
- H10W 10/30: Isolation regions comprising PN junctions
- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 16/0408: {comprising cells containing floating gate transistors (G11C16/0483, G11C16/0491 take precedence)}
- G11C 16/0466: {comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence)}
- G11C 2213/79: Array wherein the access device being a transistor
- H03K 19/0948: using CMOS {or complementary insulated gate field-effect transistors}
- H03K 19/20: characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence)
- H03K 19/21: EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
- H10B 12/20: {DRAM devices comprising floating-body transistors, e.g. floating-body cells}
- H10D 10/40: Vertical BJTs {(Vertical Heterojunction BJTs H10D10/821)}
- H10D 30/681: {having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688)}
- H10D 30/6892: {having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate}
- H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors
- H10D 30/696: {having at least one additional gate, e.g. program gate, erase gate or select gate}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/53: the imperfections being within the semiconductor body
- H10D 64/519: {characterised by their top-view geometrical layouts}
- H10D 84/859: {comprising both N-type and P-type wells, e.g. twin-tub}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/21: {of electrically active species}
- H10P 90/1906: {Preparing SOI wafers}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/061: {using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor metal-oxide-semiconductor field effect transistor (MOSFET) transistor with increased on-state current obtained through intrinsic bipolar junction transistor (BJT) of MOSFET has been described. Methods of operating the MOS transistor are provided.

## Claims

### Claim 1

A method of selectively operating a semiconductor device as a semiconductor memory device or a transistor with increased on-state drain current, said method comprising:
providing said semiconductor device comprising a substrate having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a buried layer having a second conductivity type selected from said p-type conductivity type and said n-type conductivity type and being different from said first conductivity type; a body having said first conductivity type; a source region and a drain region each having said second conductivity type and being separated by said body; and a gate positioned in between said source region and said drain region; and
selectively operating said semiconductor device as said semiconductor memory device or said transistor, wherein said selectively operating comprises:
applying a relatively low voltage to said buried layer to operate said semiconductor device as an ordinary transistor formed by said source region, said gate and said drain region;
applying a relatively high voltage to said buried layer to operate said semiconductor device as said semiconductor memory device, wherein said semiconductor memory device has at least two stable states; and
applying an intermediate high voltage higher than said relatively low voltage but lower than said relatively high voltage to said buried layer to operate said semiconductor device as said transistor with increased on-state drain current, said transistor with increased on-state current being formed by said source region, said gate and said drain region.

### Claim 2 (depends on 1)

The method of claim 1, wherein said relatively high voltage is sufficiently high to turn on a vertical bipolar junction transistor (BJT) formed by said buried layer, said body and one of said source region or said drain region.

### Claim 3 (depends on 2)

The method of claim 2, wherein said intermediate high voltage summed with a voltage applied to said gate is sufficiently high to turn on a vertical bipolar junction transistor (BJT) formed by said buried layer, said body and one of said source region or said drain region.

### Claim 4 (depends on 3)

The method of claim 3, wherein said turn on of said vertical BJT acts as a base current for a lateral BJT formed by said source region, said body and said drain region, turning on said lateral BJT and resulting in increased on-state drain current.

### Claim 5 (depends on 3)

The method of claim 3, wherein an off-state current, when said intermediate high voltage is applied, is the same as when zero voltage is applied to said buried layer.

### Claim 6 (depends on 1)

The method of claim 1, comprising applying zero voltage to said gate and applying said intermediate high voltage to said drain region, resulting in turning off a MOS transistor formed by said source region, said gate, said drain region and said body; and turning on a lateral bipolar junction transistor (BJT) formed by said source region, said body and said drain region.

### Claim 7 (depends on 6)

The method of claim 6, wherein switching between on and off of said MOS transistor is controlled by voltage applied to said gate.

### Claim 8 (depends on 1)

The method of claim 1, further comprising modulating voltage applied to said buried layer to adjust and trim a skew of said transistor.

### Claim 9 (depends on 4)

The method of claim 4, further comprising modulating voltage applied to said buried layer to compensate for change in temperature of said semiconductor device in order to comply with shifts in gate and drain voltages required to turn on said lateral BJT.

### Claim 10 (depends on 1)

The method of claim 1, wherein said semiconductor device further comprises a body contact that can be selectively connected to or isolated from said body;
wherein connection to or isolation of said body contact to or from said body is modulated by an amount of voltage applied to said buried layer.

### Claim 11 (depends on 10)

The method of claim 10, wherein application of a voltage greater than or equal to a separating threshold voltage to said buried layer forms a depletion region sufficient to isolate said body contact from said body.

### Claim 12 (depends on 11)

The method of claim 11, wherein application of a voltage greater than or equal to a separating threshold voltage to said buried layer extends a boundary of said depletion region beyond a bottom of an insulating layer separating said body contact from said body.

### Claim 13 (depends on 1)

The method of claim 1, further comprising providing a recombination region in said semiconductor device to reduce transient time between on and off states of said semiconductor device.