# US 11,908,892 B2 · Semiconductor device and formation method

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- Number: US 11,908,892 B2
- Document ID: US11908892B2
- Status: Granted
- Kind: B2
- Application number: 17/372,108
- Filed: 2021-07-09
- Published: 2022-09-29
- Granted: 2024-02-20
- Earliest claimed: 2021-03-25
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.; National Taiwan University
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.; National Taiwan University
- Inventors: Hung-Yu Ye; Yu-Shiang Huang; Chien-Te Tu; Chee-Wee Liu
- Web page: https://patentgrep.com/patent/US11908892B2

## CPC

- H10D 62/121: {oriented parallel to substrates}
- H10D 84/0128: {Manufacturing their channels}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A device comprises source/drain regions over a substrate and spaced apart along a first direction, a first gate structure between the source/drain regions, and a first channel structure surrounded by the first gate structure. The first channel structure comprises alternately stacking first semiconductor layers and second semiconductor layers. When viewed in a cross section taken along a second direction perpendicular to the first direction, central axes of the second semiconductor layers are laterally offset from central axes of the first semiconductor layers.

## Claims

### Claim 1

A device comprising:
source/drain regions over a substrate and spaced apart along a first direction;
a first gate structure between the source/drain regions; and
a first channel structure surrounded by the first gate structure, the first channel structure comprising alternately stacking first semiconductor layers and second semiconductor layers, wherein when viewed in a cross section taken along a second direction perpendicular to the first direction, central axes of the second semiconductor layers are laterally offset from central axes of the first semiconductor layers, wherein the second semiconductor layers of the first channel structure electrically connect a first one of the source/drain regions to a second one of the source/drain regions.

### Claim 2 (depends on 1)

The device of claim 1, wherein the second semiconductor layers have a smaller width than the first semiconductor layers.

### Claim 3 (depends on 1)

The device of claim 1, wherein the second semiconductor layers are made of a different material than the first semiconductor layers.

### Claim 4 (depends on 1)

The device of claim 1, wherein the second semiconductor layers have a greater germanium atomic percentage than the first semiconductor layers.

### Claim 5 (depends on 1)

The device of claim 1, wherein the second semiconductor layers have substantially a same width.

### Claim 6 (depends on 1)

The device of claim 1, wherein an upper one of the second semiconductor layers has a smaller width than a lower one of the second semiconductor layers.

### Claim 7 (depends on 1)

The device of claim 1, wherein a width difference between the second semiconductor layers is greater than a width difference between the first semiconductor layers.

### Claim 8 (depends on 1)

The device of claim 1, wherein the second semiconductor layers have different germanium atomic percentages.

### Claim 9 (depends on 1)

The device of claim 1, wherein an upper one of the second semiconductor layers has a greater germanium atomic percentage than a lower one of the second semiconductor layers.

### Claim 10 (depends on 1)

The device of claim 1, further comprising:
a second channel structure surrounded by the first gate structure, the second channel structure being symmetric with the first channel structure when viewed in the cross section taken along the second direction.

### Claim 11 (depends on 1)

The device of claim 1, further comprising:
a second channel structure being symmetric with the first channel structure when viewed in the cross section taken along the second direction;
a second gate structure surrounding the second channel structure; and
a dielectric wall separating the first gate structure from the second gate structure.

### Claim 12

A device comprising:
a source region;
a drain region separated from the source region along a first direction; and
a channel structure interposing the source region and the drain region, the channel structure comprising alternately stacking first semiconductor layers and second semiconductor layers, wherein when viewed in a cross section taken along a second direction perpendicular to the first direction, the first semiconductor layers have opposite first and second side surfaces, the second semiconductor layers have opposite third and fourth side surfaces, the third side surfaces of the second semiconductor layers are aligned with the first side surfaces of the first semiconductor layers, and the fourth side surfaces of the second semiconductor layers are laterally set back from the second side surfaces of the first semiconductor layers, wherein the second semiconductor layers of the channel structure electrically connect the source region to the drain region.

### Claim 13 (depends on 12)

The device of claim 12, wherein the second semiconductor layers non-overlap with central axes of the first semiconductor layers.

### Claim 14 (depends on 12)

The device of claim 12, wherein a width of the second semiconductor layers is less than half a width of the first semiconductor layers.

### Claim 15 (depends on 12)

The device of claim 12, wherein the fourth side surfaces of the second semiconductor layers are misaligned with each other.

### Claim 16 (depends on 12)

The device of claim 12, wherein the first semiconductor layers are germanium-free semiconductor layers, and the second semiconductor layers are germanium-containing semiconductor layers.

### Claim 17 (depends on 12)

The device of claim 12, wherein when viewed in the cross section taken along the second direction perpendicular to the first direction, the third side surfaces of the second semiconductor layers and the first side surfaces of the first semiconductor layers form a straight line interfacing a gate dielectric of a gate structure.

### Claim 18

A method comprising:
forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers over a substrate;
forming a dielectric wall on a first longitudinal side of the fin structure but not on a second longitudinal side of the fin structure;
recessing a portion of the fin structure after forming the dielectric wall;
forming an epitaxial source/drain structure on the recessed portion of the fin structure, the epitaxial source/drain structure contacting a side surface of the dielectric wall;
performing a first etching process that etches the second semiconductor layers at a faster etch rate than etching the first semiconductor layers;
after performing the first etching process, performing a second etching process to remove the dielectric wall; and
after removing the dielectric wall, forming a gate structure over the first semiconductor layers and the second semiconductor layers.

### Claim 19 (depends on 18)

The method of claim 18, wherein the first etching process etches a bottommost one of the second semiconductor layers at a faster etch rate than etching upper ones of the second semiconductor layers.

### Claim 20 (depends on 18)

The method of claim 18, wherein the second etching process etches the dielectric wall at a faster etch rate than etching the first semiconductor layers and the second semiconductor layers.