# US 11,908,891 B2 · High voltage device with gate extensions > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,908,891 B2 - Document ID: US11908891B2 - Status: Granted - Kind: B2 - Application number: 17/734,344 - Filed: 2022-05-02 - Published: 2022-08-18 - Granted: 2024-02-20 - Earliest claimed: 2019-08-29 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Jhih-Bin Chen; Ming Chyi Liu - Web page: https://patentgrep.com/patent/US11908891B2 ## CPC - H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions} - H10D 64/519: {characterised by their top-view geometrical layouts} - H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]} - H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]} - H10D 30/658: {having trench gate electrodes} - H10D 62/115: {Dielectric isolations, e.g. air gaps} - H10D 62/126: {Top-view geometrical layouts of the regions or the junctions} - H10D 62/156: {Drain regions of DMOS transistors} - H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates} - H10D 64/516: {the thicknesses being non-uniform} - H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract The present disclosure relates to a method of forming an integrated chip. The method includes forming a plurality of isolation structures within a substrate. The substrate is selectively etched to form a gate base recess within the substrate. The plurality of isolation structures are selectively etched to form a plurality of gate extension trenches extending outward from the gate base recess; forming a conductive material within the gate base recess and the plurality of gate extension trenches to form a gate electrode; and forming a source region and a drain region on opposing sides of the gate electrode. ## Claims ### Claim 1 A method of forming an integrated chip, comprising: forming a plurality of separate isolation structures within a substrate, wherein the plurality of separate isolation structures have outermost sidewalls that face one another and that are separated from one another by the substrate; selectively etching the substrate to form a gate base recess within the substrate, the gate base recess extending past the outermost sidewalls of the plurality of separate isolation structures; selectively etching the plurality of separate isolation structures to form a plurality of gate extension trenches extending outward from the gate base recess; forming a conductive material within the gate base recess and the plurality of gate extension trenches to form a gate electrode; and forming a source region and a drain region on opposing sides of the gate electrode. ### Claim 2 (depends on 1) The method of claim 1, further comprising: forming a gate dielectric along sidewalls and a recessed surface of the substrate that form the gate base recess prior to selectively etching the plurality of separate isolation structures to form the plurality of gate extension trenches. ### Claim 3 (depends on 2) The method of claim 2, further comprising: completely etching through the gate dielectric to form the plurality of gate extension trenches. ### Claim 4 (depends on 2) The method of claim 2, wherein the plurality of gate extension trenches protrude outward from a same side of the gate base recess. ### Claim 5 (depends on 2) The method of claim 2, further comprising: performing a planarization process to remove a part of the conductive material from over the substrate and to remove a part of the gate dielectric from over the substrate. ### Claim 6 (depends on 1) The method of claim 1, further comprising: selectively etching the plurality of separate isolation structures to form the gate base recess, wherein the gate base recess is defined by a sidewall and upper surface of the substrate and by a sidewall and an upper surface of the plurality of separate isolation structures. ### Claim 7 (depends on 1) The method of claim 1, further comprising: forming a silicide within a central region of the conductive material, wherein the silicide has opposing outermost edges that are laterally separated from opposing outermost edges of the conductive material by non-zero distances. ### Claim 8 (depends on 1) The method of claim 1, further comprising: selectively etching the substrate to form a plurality of isolation trenches within the substrate, wherein the plurality of separate isolation structures are formed within the plurality of isolation trenches. ### Claim 9 A method of forming an integrated chip, comprising: forming an isolation structure within a substrate; etching the substrate and the isolation structure to form a gate base recess within the substrate; forming a gate dielectric within the gate base recess and over the isolation structure; etching the gate dielectric and the isolation structure to form a gate extension trench extending outward from the gate base recess; forming a conductive material within the gate base recess and the gate extension trench; performing a planarization process to remove a part of the conductive material from over the substrate and to form a gate electrode; and forming a source region and a drain region on opposing sides of the gate electrode. ### Claim 10 (depends on 9) The method of claim 9, wherein the isolation structure comprises a first upper surface and a second upper surface after etching the isolation structure to form the gate extension trench, the second upper surface vertically over the first upper surface. ### Claim 11 (depends on 9) The method of claim 9, wherein the planarization process causes the gate electrode to have a substantially flat uppermost surface that continuously extends between opposing outermost sidewalls of the gate electrode. ### Claim 12 (depends on 9) The method of claim 9, wherein the gate electrode has a first thickness within the gate base recess and a second thickness within the gate extension trench, the first thickness being different than the second thickness. ### Claim 13 (depends on 9) The method of claim 9, wherein the gate dielectric has a bottommost surface that is coupled to opposing outermost sidewalls having different heights after performing the planarization process. ### Claim 14 (depends on 9) The method of claim 9, wherein after performing the planarization process the gate electrode laterally extends past an outermost sidewall of the gate dielectric in a first direction and the gate dielectric laterally extends past an outermost sidewall of the gate electrode in a second direction opposing the first direction. ### Claim 15 (depends on 9) The method of claim 9, wherein the gate electrode has a first thickness within the gate base recess and a second thickness within the gate extension trench, the first thickness being larger than the second thickness. ### Claim 16 A method of forming an integrated chip, comprising: forming a plurality of isolation structures within a substrate, the plurality of isolation structures being separated from one another along a first direction; etching an upper surface of the substrate to form a gate base recess having a first depth within the substrate; etching the plurality of isolation structures to form a plurality of gate extension trenches having a second depth less than the first depth, wherein the plurality of gate extension trenches extend outward from the gate base recess in a second direction that is perpendicular to the first direction; forming a gate electrode within the gate base recess and the plurality of gate extension trenches, wherein the gate electrode is formed to have a part that is below a top of the plurality of isolation structures and that continuously extends from within the gate base recess to within the plurality of gate extension trenches; and forming a source region and a drain region on opposing sides of the gate electrode. ### Claim 17 (depends on 16) The method of claim 16, further comprising: forming a gate dielectric within the gate base recess and over the upper surface of the substrate; and etching the gate dielectric to form the plurality of gate extension trenches. ### Claim 18 (depends on 16) The method of claim 16, wherein opposing outermost sidewalls of the gate electrode have different heights. ### Claim 19 (depends on 16) The method of claim 16, further comprising: forming a gate dielectric within the gate base recess, wherein the gate electrode protrudes through an opening in a sidewall of the gate dielectric to within one of the plurality of gate extension trenches. ### Claim 20 (depends on 16) The method of claim 16, further comprising: forming a gate dielectric within the gate base recess, wherein the gate electrode laterally extends past an outermost sidewall of the gate dielectric in the second direction.