# US 11,908,889 B2 · Semiconductor super-junction power device

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- Number: US 11,908,889 B2
- Document ID: US11908889B2
- Status: Granted
- Kind: B2
- Application number: 17/428,137
- Filed: 2019-12-05
- Published: 2022-09-08
- Granted: 2024-02-20
- Earliest claimed: 2019-11-27
- Assignees: Suzhou Oriental Semiconductor Co., Ltd.
- Applicants: Suzhou Oriental Semiconductor Co., Ltd.
- Inventors: Yi Gong; Wei Liu; Yuanlin Yuan; Lei Liu; Rui Wang
- Web page: https://patentgrep.com/patent/US11908889B2

## CPC

- H10D 62/111: {Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures}
- H10D 30/68: Floating-gate IGFETs
- H10D 84/143: {the built-in components being PN junction diodes}
- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Provided is a semiconductor super junction power device. The semiconductor super junction power device includes an MOSFET cell array composed of multiple super junction MOSFET cells. Each of multiple MOSFET cells includes a p-type body region located at the top of an n-type drift region, a p-type columnar doping region located below the p-type body region, an n-type source region located in the p-type body region, a gate dielectric layer located above the p-type body region, a gate electrode located above the p-type body region, an n-type floating gate located above the p-type body region and an opening located in the gate dielectric layer, where in a lateral direction, the gate electrode is located on one side close to the n-type source region; an opening located in the gate dielectric layer, where the n-type floating gate contacts the p-type body region through the opening to form a p-n junction diode.

## Claims

### Claim 1

A semiconductor super junction power device, comprising:
an n-type drain region, an n-type drift region located above the n-type drain region and a super junction MOSFET cell array composed of a plurality of super junction MOSFET cells, wherein each super junction MOSFET cell of the plurality of super junction MOSFET cells comprises:
a p-type body region, located at a top of the n-type drift region;
a p-type columnar doping region, located below the p-type body region;
an n-type source region, located in the p-type body region;
a gate structure located above the p-type body region, wherein the gate structure comprises a gate dielectric layer, a gate electrode and an n-type floating gate, the gate electrode and the n-type floating gate are located above the gate dielectric layer, and in a lateral direction, the gate electrode is located on a side close to the n-type source region, the n-type floating gate is located on a side close to the n-type drift region, and the gate electrode is configured to act on the n-type floating gate through capacitive coupling; and
an opening located in the gate dielectric layer, wherein the n-type floating gate contacts the p-type body region through the opening to form a p-n junction diode.

### Claim 2 (depends on 1)

The semiconductor super junction power device of claim 1, wherein the gate electrode extends to be above the n-type floating gate.

### Claim 3 (depends on 1)

The semiconductor super junction power device of claim 1, wherein the gate electrode extends to be above the n-type floating gate and covers a sidewall of the n-type floating gate close to the n-type drift region.

### Claim 4 (depends on 1)

The semiconductor super junction power device of claim 1, wherein the opening is located below the n-type floating gate and on a side of the n-type floating gate close to the n-type drift region.

### Claim 5 (depends on 1)

The semiconductor super junction power device of claim 1, wherein in the super junction MOSFET cell array, a gate electrode of at least one super junction MOSFET cell of the plurality of super junction MOSFET cells is electrically connected to the n-type source region.