# US 11,908,876 B2 · Semiconductor device including photoelectric conversion element > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,908,876 B2 - Document ID: US11908876B2 - Status: Granted - Kind: B2 - Application number: 17/517,705 - Filed: 2021-11-03 - Published: 2022-03-10 - Granted: 2024-02-20 - Earliest claimed: 2014-06-09 - Assignees: Semiconductor Energy Laboratory Co., Ltd. - Applicants: Semiconductor Energy Laboratory Co., Ltd. - Inventors: Yuki Okamoto; Yoshiyuki Kurokawa; Hiroki Inoue; Takuro Ohmaru - Web page: https://patentgrep.com/patent/US11908876B2 ## CPC - H10F 39/802: {Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes} - H04N 23/54: Mounting of pick-up tubes, electronic image sensors, deviation or focusing coils - H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate} - H10D 84/0126: {the components including insulated gates, e.g. IGFETs} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/83: of only insulated-gate FETs [IGFET] - H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO} - H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors} - H10D 86/60: wherein the TFTs are in active matrices - H10F 10/17: Photovoltaic cells having only PIN junction potential barriers - H10F 39/016: {of thin-film-based image sensors} - H10F 39/12: Image sensors - H10F 39/18: Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors - H10F 39/803: {Pixels having integrated switching, control, storage or amplification elements} - H10F 39/8033: {Photosensitive area} - H10F 39/8037: {the integrated elements comprising a transistor} - H10F 39/80377: {characterised by the channel of the transistor, e.g. channel having a doping gradient} - H10F 39/807: {Pixel isolation structures} - H10W 20/427: {Power or ground buses} - Y02E 10/548: Amorphous silicon PV cells - H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - Y02E: REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION ## Abstract A solid-state imaging device with high productivity and improved dynamic range is provided. In the imaging device including a photoelectric conversion element having an i-type semiconductor layer, functional elements, and a wiring, an area where the functional elements and the wiring overlap with the i-type semiconductor in a plane view is preferably less than or equal to 35%, further preferably less than or equal to 15%, and still further preferably less than or equal to 10% of the area of the i-type semiconductor in a plane view. Plural photoelectric conversion elements are provided in the same semiconductor layer, whereby a process for separating the respective photoelectric conversion elements can be reduced. The respective i-type semiconductor layers in the plural photoelectric conversion elements are separated by a p-type semiconductor layer or an n-type semiconductor layer. ## Claims ### Claim 1 A semiconductor device comprising: a photoelectric conversion element; a first transistor, a second transistor, a third transistor, and a fourth transistor; a first wiring electrically connected to a gate of the first transistor; a second wiring electrically connected to a gate of the second transistor; a third wiring electrically connected to a gate of the fourth transistor; and a fourth wiring electrically connected to the photoelectric conversion element, wherein one of a source and a drain of the first transistor is electrically connected to the photoelectric conversion element, wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor and a gate of the third transistor, wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor, wherein, in a plan view, a conductive layer functioning as the fourth wiring is provided in a net shape, wherein, in the plan view, the conductive layer functioning as the fourth wiring surrounds the first transistor, the second transistor, the third transistor, and the fourth transistor, and wherein, in the plan view, the conductive layer functioning as the fourth wiring does not overlap with a semiconductor layer of each of the first transistor, the second transistor, the third transistor, and the fourth transistor. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein each of the first transistor, the second transistor, the third transistor, and the fourth transistor comprises a channel formation region comprising an oxide semiconductor. ### Claim 3 A semiconductor device comprising: a photoelectric conversion element; a first transistor, a second transistor, a third transistor, and a fourth transistor; a first wiring electrically connected to a gate of the first transistor; a second wiring electrically connected to a gate of the second transistor; a third wiring electrically connected to a gate of the fourth transistor; a fourth wiring electrically connected to the photoelectric conversion element; and a capacitor, wherein one of a source and a drain of the first transistor is electrically connected to the photoelectric conversion element, wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor and a gate of the third transistor, wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor, wherein one electrode of the capacitor is electrically connected to the other of the source and the drain of the first transistor, wherein, in a plan view, a conductive layer functioning as the fourth wiring is provided in a net shape, wherein, in the plan view, the conductive layer functioning as the fourth wiring surrounds the first transistor, the second transistor, the third transistor, and the fourth transistor, and wherein, in the plan view, the conductive layer functioning as the fourth wiring does not overlap with a semiconductor layer of each of the first transistor, the second transistor, the third transistor, and the fourth transistor. ### Claim 4 (depends on 3) The semiconductor device according to claim 3, wherein each of the first transistor, the second transistor, the third transistor, and the fourth transistor comprises a channel formation region comprising an oxide semiconductor.