# US 11,908,873 B2 · Active matrix substrate, display device, and motherboard > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,908,873 B2 - Document ID: US11908873B2 - Status: Granted - Kind: B2 - Application number: 17/270,399 - Filed: 2018-08-23 - Published: 2021-07-22 - Granted: 2024-02-20 - Earliest claimed: 2018-08-23 - Assignees: Sharp Kabushiki Kaisha - Applicants: Sharp Kabushiki Kaisha - Inventors: Tohru Okabe; Ryosuke Gunji; Shinji Ichikawa; Shinsuke Saida; Shoji Okazaki; Tokuo Yoshida; Hiroki Taniyama; Kohji Ariga; Hiroharu Jinmura; Akira Inoue; Yoshihiro Nakada; Yoshihiro Kohara; Koji Tanimura - Web page: https://patentgrep.com/patent/US11908873B2 ## CPC - H10D 86/0231: {using masks, e.g. half-tone masks} - H10D 86/60: wherein the TFTs are in active matrices - G09F 9/00: Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements (in which the variable information is permanently attached to a movable support G09F11/00; abacus G06C1/00; slide-rules G06G1/00) - G09F 9/30: in which the desired character or characters are formed by combining individual elements (panels comprising a number of electrodes in a single cell controlling light arriving from an independent light source, e.g. electro-optical or magneto-optical cell, G02F1/00) - H10D 86/441: {Interconnections, e.g. scanning lines} - H10D 86/443: {adapted for preventing breakage, peeling or short circuiting} - H10D 89/611: {using diodes as protective elements} - H10D 89/811: {using FETs as protective elements} - H10K 59/131: Interconnections, e.g. wiring lines or terminals - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - G09F: DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS - H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES ## Abstract An active matrix substrate including a resin substrate including a plurality of external connection terminals arranged near a display region, the active matrix substrate includes: a plurality of first lead wires each extending from one of the external connection terminals to the display region; and a plurality of second lead wires each extending from one of the external connection terminals to a separation line, the second lead wires being arranged with an arrangement pitch along the separation line, and the arrangement pitch of the second lead wires being greater than an arrangement pitch of the first lead wires. ## Claims ### Claim 1 An active matrix substrate including a resin substrate having a plurality of external connection terminals arranged near a display region, the active matrix substrate comprising: a plurality of first lead wires, each first lead wire extending from one of the plurality of external connection terminals to the display region; and a plurality of second lead wires, each second lead wire extending from one of the plurality of external connection terminals to a separation line, the plurality of second lead wires being arranged with an arrangement pitch along the separation line, and the arrangement pitch of the plurality of second lead wires being greater than an arrangement pitch of the plurality of first lead wires. ### Claim 2 (depends on 1) The active matrix substrate according to claim 1, further comprising: a first inorganic insulating film and a planarization film stacked on top of one another in a stated order on the plurality of second lead wires, the planarization film being made of resin; and a slit formed of the first inorganic insulating film along the separation line across the plurality of second lead wires in a plan view, the slit exposing the plurality of second lead wires, wherein along the separation line across the plurality of second lead wires in a plan view, the planarization film fills the slit to cover the plurality of second lead wires. ### Claim 3 (depends on 2) The active matrix substrate according to claim 2, further comprising a second inorganic insulating film below, and in contact with, the second lead wire, wherein the resin substrate is below the second inorganic insulating film. ### Claim 4 (depends on 3) The active matrix substrate according to claim 3, wherein the plurality of second lead wires across the separation line are conductive, and formed of a same material as a semiconductor layer is formed. ### Claim 5 (depends on 2) The active matrix substrate according to claim 2, wherein the plurality of second lead wires include a portion that is made of a metal film formed of a same material, and in a same layer, as a metal wire in the display region is formed. ### Claim 6 (depends on 1) The active matrix substrate according to claim 1, further comprising a terminal transistor formed on the plurality of second lead wires and provided between the plurality of external connection terminals and the separation line, the terminal transistor having a gate terminal and a source terminal electrically connected together. ### Claim 7 (depends on 1) A display device, comprising the active matrix substrate according to claim 1, wherein the separation line coincides with an end face of a display panel included in the display device. ### Claim 8 (depends on 1) Another substrate comprising a plurality of active matrix substrates planarly arranged and including the active matrix substrate according to claim 1. ### Claim 9 (depends on 8) The mother substrate according to claim 8, wherein each of the plurality of active matrix substrates includes a short ring, so such that the plurality of second lead wires of the active matrix substrate extends across the separation line from the plurality of external connection terminals and connects to the short ring. ### Claim 10 (depends on 9) The mother substrate according to claim 9, wherein the short ring is provided in common with neighboring active matrix substrates included in the plurality of active matrix substrates. ### Claim 11 (depends on 9) The mother substrate according to claim 9, wherein the short ring is shaped into frames, each frame is provided around one of the active matrix substrates. ### Claim 12 (depends on 9) The mother substrate according to claim 9, further comprising a ring transistor provided to the plurality of second lead wires and formed between the separation line and the short ring, the ring transistor having a gate terminal and a source terminal electrically connected together. ### Claim 13 (depends on 12) The mother substrate according to claim 12, wherein the short ring is dual-redundant and includes a first short ring and a second short ring, and the ring transistor includes: a first ring transistor formed between neighboring second lead wires that are included in the plurality of second lead wires, having a source terminal and a gate terminal electrically connected to one of the neighboring second lead wires, and having a drain terminal electrically connected to another one of the neighboring second lead wires; and a second ring transistor having a source terminal and a gate terminal electrically connected to the other one of the neighboring second lead wires, and a drain terminal electrically connected to the one of the neighboring second lead wires. ### Claim 14 (depends on 13) The mother substrate according to claim 13, wherein each of the plurality of active matrix substrates has a side not facing the plurality of external connection terminals, the side being provided with a first connection wire and a second connection wire running in parallel with the side and respectively extending from the first short ring and the second short ring, and each of the first connection wire and the second connection wire partially includes an intrinsic semiconductor layer including a diode transistor having a source terminal and a gate terminal of the diode transistor electrically connected together.