# US 11,908,867 B2 · Semiconductor device and method for fabricating the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,908,867 B2 - Document ID: US11908867B2 - Status: Granted - Kind: B2 - Application number: 18/157,591 - Filed: 2023-01-20 - Published: 2023-05-25 - Granted: 2024-02-20 - Earliest claimed: 2019-07-17 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Myoung-Sun Lee; Keun Hwi Cho - Web page: https://patentgrep.com/patent/US11908867B2 ## CPC - H10D 84/853: {comprising FinFETs} - H10D 30/62: Fin field-effect transistors [FinFET] - H10D 84/0151: {Manufacturing their isolation regions} - H10D 84/0158: {the components including FinFETs} - H10D 84/0188: {Manufacturing their isolation regions} - H10D 84/0193: {the components including FinFETs} - H10D 89/10: Integrated device layouts - H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain} - H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)} - H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions - H10D 64/259: {Source or drain electrodes being self-aligned with the gate electrode and having bottom surfaces higher than the interface between the channel and the gate dielectric} - H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10P 14/3408: {Silicon carbide} - H10P 14/3411: {Silicon, silicon germanium or germanium} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract There is provided a semiconductor device having enhanced operation performance by utilizing a cut region where a gate cut is implemented. There is provided a semiconductor device comprising a first active pattern, a second active pattern, a third active pattern, and a fourth active pattern, all of which extend in parallel in a first direction, and are arranged along a second direction intersecting the first direction; a first gate electrode extended in the second direction on the first to fourth active patterns a first cut region extended in the first direction between the first active pattern and the second active pattern to cut the first gate electrode and a second cut region extended in the first direction between the third active pattern and the fourth active pattern to cut the first gate electrode, wherein one or more first dimensional features related to the first cut region is different from one or more second dimensional features related to the second cut region. ## Claims ### Claim 1 A semiconductor device comprising: a first active pattern, a second active pattern, a third active pattern, and a fourth active pattern, all of which extend in parallel in a first direction, and are arranged along a second direction intersecting the first direction; a field insulating film covering a part of side surfaces of the first to fourth active patterns; a gate electrode provided on the first to fourth active patterns and extending in the second direction; a gate dielectric film interposed between the first to fourth active patterns and the gate electrode, and between the field insulating film and the gate electrode; a first cut region that extends from a top surface of the gate electrode into the field insulating film between the first active pattern and the second active pattern to cut the gate electrode and the gate dielectric film; and a second cut region that extends from the top surface of the gate electrode into the field insulating film between the third active pattern and the fourth active pattern to cut the gate electrode and the gate dielectric film, wherein a first width of the first cut region in the second direction at the top surface of the gate electrode is different from a second width of the second cut region in the second direction at the top surface of the gate electrode, wherein a first length of the first cut region from a bottom surface of the first cut region to the top surface of the gate electrode is different from a second length of the second cut region from a bottom surface of the second cut region to the top surface of the gate electrode, and wherein the first length of the first cut region and the second length of the second cut region are longer than a third length from a top surface of the field insulating film to the top surface of the gate electrode. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the first width of the first cut region in the second direction at the top surface of the gate electrode is shorter than the second width of the second cut region in the second direction at the top surface of the gate electrode, and wherein the first length of the first cut region from the top surface of the gate electrode is higher than the second length of the second cut region from the top surface of the gate electrode. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein the first cut region and the second cut region comprise at least one of silicon nitride, silicon oxynitride, silicon oxide, or silicon oxy carbonitride. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein the first cut region extends in the first direction between the first active pattern and the second active pattern, wherein the second cut region extends in the first direction between the third active pattern and the fourth active pattern, and wherein the first length of the first cut region extended in the first direction is different from the second length of the second cut region extended in the first direction. ### Claim 5 (depends on 4) The semiconductor device of claim 4, wherein the first and second active patterns correspond to an N-Channel Field Effect Transistor (NFET) region, and the third and fourth active patterns correspond to a P-Channel Field Effect Transistor (PFET) region, and wherein the length of the first cut region extended in the first direction is longer than the second length of the second cut region extended in the first direction. ### Claim 6 (depends on 1) The semiconductor device of claim 1, wherein the first cut region extends in the first direction between the first active pattern and the second active Pattern, wherein the second cut region extends in the first direction between the third active pattern and the fourth active pattern, and wherein the first and second active patterns correspond to an N-Channel Field Effect Transistor (NFET) region, and the third and fourth active patterns correspond to a P-Channel Field Effect Transistor (PFET) region. ### Claim 7 (depends on 1) The semiconductor device of claim 1, wherein the first and second active patterns correspond to an N-Channel Field Effect Transistor (NFET) region, and the third and fourth active patterns correspond to a P-Channel Field Effect Transistor (PFET) region, and wherein a first distance between the second active pattern and the first cut region is longer than a second distance between the third active pattern and the second cut region. ### Claim 8 (depends on 1) The semiconductor device of claim 1, wherein a distance between the first active pattern and the first cut region is same as a distance between the first cut region and the second active pattern, and wherein a distance between the third active pattern and the second cut region is same as a distance between the second cut region and the fourth active pattern. ### Claim 9 (depends on 1) The semiconductor device of claim 1, wherein the gate electrode comprises a work function adjustment film extending along the gate dielectric film and a filling conductive film on the work function adjustment film. ### Claim 10 (depends on 1) The semiconductor device of claim 1, wherein the gate dielectric film is not extended along a side surface of the first cut region and a side surface of the second cut region. ### Claim 11 A semiconductor device comprising: a first active pattern, a second active pattern, a third active pattern, and a fourth active pattern, all of which extend in parallel in a first direction, and are arranged along a second direction intersecting the first direction; a field insulating film surrounding a part of side surfaces of the first to fourth active pattern, a first gate electrode provided on the first to fourth active patterns and extending in the second direction; a first gate dielectric film interposed between the first to fourth active patterns and the first gate electrode, and between the field insulating film and the first gate electrode; a first cut region that extends in the first direction between the first active pattern and the second active pattern to cut the first gate electrode and the first gate dielectric film; a second cut region that extends in the first direction between the third active pattern and the fourth active pattern to cut the first gate electrode and the first gate dielectric film; and a third cut region that extends in the first direction between the second active pattern and the third active pattern to cut the first gate electrode and the first gate dielectric film, wherein a first width of the first cut region in the second direction at the top surface of the first gate electrode, a second width of the second cut region in the second direction at the top surface of the first gate electrode, and a third width of the third cut region in the second direction at the top surface of the first gate electrode are different from each other, wherein a first length of the first cut region from a bottom surface of the first cut region to the top surface of the first gate electrode, a second length of the second cut region from a bottom surface of the second cut region to the top surface of the first gate electrode, and a third length of the third cut region from a bottom surface of the third cut region to the top surface of the first gate electrode are different from each other, and wherein the first length of the first cut region, the second length of the second cut region, and the third length of the third cut region are higher than a fourth length from a top surface of the field insulating film to the top surface of the first gate electrode. ### Claim 12 (depends on 11) The semiconductor device of claim 11, wherein the third width of the third cut region in the second direction at the top surface of the first gate electrode is larger than the first width of the first cut region in the second direction at the top surface of the first gate electrode and is shorter than the second width of the second cut region in the second direction at the top surface of the first gate electrode, and wherein the third length of the third cut region from the top surface of the first gate electrode is lower than the first length of the first cut region from the top surface of the first gate electrode and is higher than the second length of the second cut region from the top surface of the first gate electrode. ### Claim 13 (depends on 11) The semiconductor device of claim 11, wherein further comprising: a second gate electrode extended in the second direction adjacent to the first gate electrode on the first to fourth active patterns; and a second gate dielectric film interposed between the first to fourth active patterns and the second gate electrode, and between the field insulating film and the second gate electrode, wherein the first cut region and the second cut region cut the second gate electrode and the second gate dielectric film. ### Claim 14 (depends on 11) The semiconductor device of claim 11, wherein a first distance between the second active pattern and the third cut region is different from a second distance between the third active pattern and the third cut region. ### Claim 15 (depends on 14) The semiconductor device of claim 14, wherein the first and second active patterns correspond to an N-Channel Field Effect Transistor (NFET) region, and the third and fourth active patterns correspond to a P-Channel Field Effect Transistor (PFET) region, and wherein a first distance between the second active pattern and the third cut region is different from a second distance between the third active pattern and the third cut region. ### Claim 16 (depends on 15) The semiconductor device of claim 15, wherein the first and second active patterns correspond to an N-Channel Field Effect Transistor (NFET) region, and the third and fourth active patterns correspond to a P-Channel Field Effect Transistor (PFET) region, and wherein a first distance between the second active pattern and the third cut region is shorter from a second distance between the third active pattern and the third cut region. ### Claim 17 (depends on 14) The semiconductor device of claim 14, wherein the first cut region, the second cut region and the third cut region include at least one of silicon nitride, silicon oxynitride, silicon oxide, or silicon oxy carbonitride. ### Claim 18 A semiconductor device, comprising: a first active pattern extending in a first direction; a second active pattern extending in the first direction; a field insulating film surrounding a part of side surfaces of the first and second active patterns on the substrate; a first gate electrode provided on the first and second active patterns and extending in a second direction intersecting the first direction; a first cut region provided on a first side surface of the first active pattern opposite to the second active pattern and extending in the first direction to cut the gate electrode; and a second cut region provided on a second side surface of the second active pattern opposite to the first active pattern and extending in the first direction to cut the gate electrode, wherein the first and second active patterns protrude upwardly above the field insulating film, wherein a first width of the first cut region in the second direction at a top surface of the first gate electrode is different from a second width of the second cut region in the second direction at the top surface of the first gate electrode, wherein a first length of the first cut region from a bottom surface of the first cut region to the top surface of the first gate electrode is different from a second length of the second cut region from a bottom surface of the second cut region to the top surface of the first gate electrode, and wherein the first length of the first cut region and the second length of the second cut are higher than a third length from a top surface of the field insulating film to the top surface of the first gate electrode. ### Claim 19 (depends on 18) The semiconductor device of claim 18, further comprising: a second gate electrode provided on the first and second active patterns and extending in the second direction adjacent to the first gate electrode; and a third cut region that extends in the first direction between the first active pattern and the second active pattern to cut the second gate electrode, and not to cut the first gate electrode. ### Claim 20 (depends on 19) The semiconductor of claim 19, wherein a top surface of the second gate electrode is on a same plane as the top surface of the first gate electrode, wherein a third width of the third cut region in the second direction at the top surface of the second gate electrode is different from the first width of the first cut region in the second direction at the top surface of the first gate electrode and the second width of the second cut region in the second direction at the top surface of the first gate electrode, wherein a fourth length of the third cut region from the bottom surface of the third cut region to the top surface of the second gate electrode is different from the first length of the first cut region and the second length of the second cut region, and wherein the fourth length of the third cut region is higher than the third length from the top surface of the field insulating film to the top surface of the first gate electrode.