# US 11,908,864 B2 · Method of manufacturing semiconductor devices and a semiconductor device

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- Number: US 11,908,864 B2
- Document ID: US11908864B2
- Status: Granted
- Kind: B2
- Application number: 17/516,110
- Filed: 2021-11-01
- Published: 2022-02-24
- Granted: 2024-02-20
- Earliest claimed: 2018-06-26
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chun-Hung Chen; Chih-Hung Hsieh; Jhon Jhy Liaw
- Web page: https://patentgrep.com/patent/US11908864B2

## CPC

- H10D 84/853: {comprising FinFETs}
- H10D 84/0191: {Manufacturing their doped wells}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/854: {comprising arrangements for preventing bipolar actions between the different IGFET regions, e.g. arrangements for latchup prevention}
- H10D 84/859: {comprising both N-type and P-type wells, e.g. twin-tub}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/209: {in silicon to make buried insulating layers}
- H10P 30/21: {of electrically active species}
- H10P 30/22: using masks
- H10P 30/222: {characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221)}
- H10P 30/28: characterised by an annealing step, e.g. for activation of dopants
- H10W 10/031: {of isolation regions comprising PN junctions}
- H10W 10/30: Isolation regions comprising PN junctions
- H10P 30/208: {of electrically inactive species}
- H10P 30/221: {characterised by the angle between the ion beam and the mask}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

In a method of manufacturing a semiconductor device, a first-conductivity type implantation region is formed in a semiconductor substrate, and a carbon implantation region is formed at a side boundary region of the first-conductivity type implantation region.

## Claims

### Claim 1

A semiconductor device comprising:
a semiconductor substrate;
a first fin structure protruding from the semiconductor substrate;
a second fin structure protruding from the semiconductor substrate; and
a carbon barrier region disposed at a region of the semiconductor substrate between the first fin structure and the second fin structure
wherein the carbon barrier region extends to a bottom of each of the first and second fin structures.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising:
a first p-type well region in the semiconductor substrate below the first fin structure; and
a first n-type well region in the semiconductor substrate below the second fin structure,
wherein the carbon barrier region is disposed at a boundary region between the first p-type well region and the first n-type well region.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein a doping concentration of the carbon barrier region is in a range from 1×1018 cm−1 to 2×1019 cm−3.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein:
the first p-type well region includes a lower p-well region and an upper p-well region disposed over the lower p-well region, and
the carbon barrier region is disposed at a boundary region of the lower p-well region and the first n-type well region.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein a dopant concentration of the upper p-well region is smaller than a dopant concentration of the lower p-well region.

### Claim 6 (depends on 2)

The semiconductor device of claim 2, further comprising:
a p-type anti-punch-through region disposed at the first fin structure; and
an n-type anti-punch-through region disposed at the second fin structure.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein a first field effect transistor (FET) is disposed over the p-type anti-punch-through region and a second FET is disposed over the n-type anti-punch-through region.

### Claim 8 (depends on 2)

The semiconductor device of claim 2, wherein the carbon barrier region overlaps the first p-type well region and the first n-type well region.

### Claim 9

A semiconductor device comprising:
a semiconductor substrate;
a first first-conductive type fin structure protruding from the semiconductor substrate;
a second first-conductive type fin structure protruding from the semiconductor substrate;
a first gate structure covering first channel regions of the first and second first-conductive type fin structures, the first channel regions being above an isolation insulating layer;
a first second-conductive type fin structure protruding from the semiconductor substrate;
a second second-conductive type fin structure protruding from the semiconductor substrate;
a second gate structure covering second channel regions of the first and second second-conductive type fin structures, the second channel regions being above the isolation insulating layer; and
a carbon barrier region disposed at a region of the semiconductor substrate between the second first-conductive type fin structure and the first second-conductive type fin structure
wherein the carbon barrier region extends to a bottom of each of the second first-conductive type fin structure and the first second-conductive type fin structure.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, further comprising:
a first first-conductive type well region in the semiconductor substrate below the first and second first-conductive type fin structures; and
a first second-conductive type well region in the semiconductor substrate below the first and second second-conductive type fin structures,
wherein the carbon barrier region is disposed at a boundary region between the first first-conductive type well region and the first second-conductive type well region.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein a depth D1 from a bottom of the isolation insulating layer to a bottom of the carbon barrier region is in a range from 50 nm to 100 nm.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein:
the first first-conductive type well region includes a lower well region and an upper well region disposed over the lower well region, and
the carbon barrier region is disposed at a boundary region of the lower well region and the first second-conductive type well region.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein a dopant concentration of the upper well region is smaller than a dopant concentration of the lower well region.

### Claim 14 (depends on 10)

The semiconductor device of claim 10, further comprising:
a first anti-punch-through region disposed at each of the first and second first-conductive type fin structures; and
a second anti-punch-through region disposed at each of the first and second second-conductive type fin structures.

### Claim 15 (depends on 10)

The semiconductor device of claim 10, wherein the carbon barrier region overlaps the first first-conductive type well region and the first second-conductive type well region.

### Claim 16 (depends on 10)

The semiconductor device of claim 10, wherein each of the first and second channel regions includes multiple semiconductor layers vertically stacked.

### Claim 17 (depends on 10)

The semiconductor device of claim 10, wherein no carbon barrier region is disposed between the first first-conductive type fin structure and the second first-conductive type fin structure, and between the first second-conductive type fin structure and the second second-conductive type fin structure.

### Claim 18

A semiconductor device including a static random access memory (SRAM), the SRAM comprising:
an n-channel fin field effect transistor (FinFET) having a first fin structure disposed over a semiconductor substrate;
a p-channel FinFET having a second fin structure disposed over the substrate;
a p-type well formed in the semiconductor substrate;
an n-type well formed in the semiconductor substrate; and
a carbon barrier region disposed at a boundary region in the semiconductor substrate between the p-type well and the n-type well,
wherein a bottom of each of the first and second fin structures includes carbon in an amount of 1×1018 atoms·cm−3 to 2×1019 atoms·cm−3.

### Claim 19 (depends on 18)

The semiconductor device of claim 18, wherein:
a first p-type implantation region is formed in the first fin structure, and a first n-type implantation region is formed in the second fin structure.

### Claim 20 (depends on 19)

The semiconductor device of claim 19, wherein:
a second p-type implantation region is formed between the p-type well and the first p-type implantation region, and
a lower part of the second p-type implantation region is located in the semiconductor substrate, and an upper part of the second p-type implantation region is located in the first fin structure.