# US 11,908,863 B2 · Transistor element, ternary inverter apparatus comprising same, and method for producing same

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- Number: US 11,908,863 B2
- Document ID: US11908863B2
- Status: Granted
- Kind: B2
- Application number: 17/419,700
- Filed: 2019-12-16
- Published: 2022-03-17
- Granted: 2024-02-20
- Earliest claimed: 2018-12-31
- Assignees: Unist (Ulsan National Institute of Science and Technology)
- Applicants: Unist(Ulsan National Institute of Science and Technology)
- Inventors: Kyung Rok Kim; Jae Won Jeong; Young Eun Choi; Woo Seok Kim; Jiwon Chang
- Web page: https://patentgrep.com/patent/US11908863B2

## CPC

- H10D 30/0241: {doping of vertical sidewalls, e.g. using tilted or multi-angled implants}
- H10D 84/853: {comprising FinFETs}
- H10D 30/022: {having lightly-doped source or drain extensions selectively formed at the sides of the gates}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 62/17: Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D 84/0165: {the components including complementary IGFETs, e.g. CMOS devices}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A transistor device includes a substrate, a fin structure extending on the substrate in a direction parallel to a top surface of the substrate, a source region and a drain region provided at an upper portion of the fin structure, a constant current generating layer provided at a lower portion of the fin structure, a gate insulating film provided on both side surfaces and a top surface of the upper portion of the fin structure, and a gate electrode provided on the gate insulating film, wherein the gate electrode is provided on the fin structure and between the source region and the drain region, the constant current generating layer generates a constant current between the drain region and the substrate, and the constant current is independent from a gate voltage applied to the gate electrode.

## Claims

### Claim 1

A transistor device comprising:
a substrate;
a fin structure extending on the substrate in a direction parallel to a top surface of the substrate;
a source region and a drain region provided at an upper portion of the fin structure;
a constant current generating layer provided at a lower portion of the fin structure;
a gate insulating film provided on both side surfaces and a top surface of the upper portion of the fin structure; and
a gate electrode provided on the gate insulating film,
wherein the gate electrode is provided on the fin structure and between the source region and the drain region,
the substrate and the constant current generating layer have a first conductivity type,
the source region and the drain region have a second conductivity type that is different from the first conductivity type,
the constant current generating layer generates a constant current between the drain region and the substrate, and an electric field is formed between the drain region and the constant current generating layer, and
the constant current is independent from a gate voltage applied to the gate electrode.

### Claim 2 (depends on 1)

The transistor device of claim 1, wherein the constant current generating layer is electrically connected to a lower portion of the source region and a lower portion of the drain region.

### Claim 3 (depends on 1)

The transistor device of claim 1, wherein the constant current generating layer directly contacts a bottom surface of the source region and a bottom surface of the drain region.

### Claim 4 (depends on 1)

The transistor device of claim 1, wherein a doping concentration of the constant current generating layer is 3×1018 cm−3 or greater.

### Claim 5 (depends on 1)

The transistor device of claim 1, wherein
an intensity of the electric field is 106 V/cm or greater.

### Claim 6

A ternary inverter device comprising:
an NMOS transistor device; and
a PMOS transistor device,
wherein each of the NMOS transistor device and the PMOS transistor device comprises:
a substrate;
a fin structure extending on the substrate in a direction parallel to a top surface of the substrate;
a source region and a drain region provided at an upper portion of the fin structure; and
a constant current generating layer provided under the fin structure,
wherein the constant current generating layer directly contacts a lower portion of the source region and a lower portion of the drain region, and generates a constant current between the drain region and the substrate,
the drain region of the NMOS transistor device and the drain region of the PMOS transistor device have identical voltages, and
in each of the NMOS transistor device and the PMOS transistor device, the substrate and the constant current generating layer have a conductivity type identical to each other, and the source region and the drain region have another conductivity type identical to each other, and an electric field is formed between the drain region and the constant current generating layer.

### Claim 7 (depends on 6)

The ternary inverter device of claim 6, wherein each of the NMOS transistor device and the PMOS transistor device further comprises:
a gate insulating film provided on both side surfaces and a top surface of the upper portion of the fin structure; and
a gate electrode provided on the gate insulating film, wherein the constant current is independent from a gate voltage applied to the gate electrode.

### Claim 8 (depends on 6)

The ternary inverter device of claim 6, wherein
the drain region of the NMOS transistor device and the drain region of the PMOS transistor device
have a first voltage when the NMOS transistor device has a channel current that is stronger than the constant current and the PMOS transistor device has the constant current that is stronger than a channel current,
have a second voltage when the NMOS transistor device has the constant current that is stronger than the channel current and the PMOS transistor device has the channel current that is stronger than the constant current, and
have a third voltage when each of the NMOS transistor device and the PMOS transistor device has the constant current that is stronger than the channel current,
wherein the second voltage is greater than the first voltage, and
the third voltage has a value between the first voltage and the second voltage.

### Claim 9 (depends on 6)

The ternary inverter device of claim 6, wherein in each of the NMOS transistor device and the PMOS transistor device, and a doping concentration of the constant current generating layer is greater than a doping concentration of the substrate.

### Claim 10 (depends on 6)

The ternary inverter device of claim 6, wherein in each of the NMOS transistor device and the PMOS transistor device, a doping concentration of the constant current generating layer is 3×1018 cm−3 or greater.

### Claim 11

A method of manufacturing a transistor device, the method comprising:
forming, on a substrate, a fin structure extending in a first direction;
forming a constant current generating layer at a lower portion of the fin structure;
forming, on the substrate, a gate electrode extending in a second direction that intersects the first direction;
forming a gate insulating film between the gate electrode and the fin structure; and
forming, on the fin structure, a source region and a drain region that are spaced apart from each other in the first direction,
wherein the constant current generating layer has a conductivity type identical to a conductivity type of the substrate,
the source region and the drain region are spaced apart from each other with the gate electrode therebetween, and
the forming of the constant current generating layer comprises:
forming a pair of impurity films on both sides of the lower portion of the fin structure, respectively; and
heat-treating the pair of impurity films.

### Claim 12 (depends on 11)

The method of claim 11, wherein the pair of impurity films include a boron silicate glass (BSG) film or a phosphorus silicate glass (PSG) film.

### Claim 13 (depends on 11)

The method of claim 11, wherein the forming of the constant current generating layer comprises:
implanting an impurity into the lower portion of the fin structure by using an ion implantation process.