# US 11,908,862 B2 · FinFET and fabrication method thereof

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- Number: US 11,908,862 B2
- Document ID: US11908862B2
- Status: Granted
- Kind: B2
- Application number: 16/707,042
- Filed: 2019-12-09
- Published: 2020-04-09
- Granted: 2024-02-20
- Earliest claimed: 2016-05-05
- Assignees: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Applicants: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Inventors: Yong Li
- Web page: https://patentgrep.com/patent/US11908862B2

## CPC

- H10D 84/853: {comprising FinFETs}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8312: {the IGFETs characterised by having different source or drain region structures, e.g. IGFETs having symmetrical source or drain regions integrated with IGFETs having asymmetrical source or drain regions}
- H10P 50/642: {Chemical etching}
- H10P 50/692: {characterised by their composition, e.g. multilayer masks or materials}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10P 50/242: {of Group IV materials}
- H10P 50/283: {by chemical means}
- H10P 50/693: {characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A FinFET is provided. The FinFET includes a substrate including an NMOS (N-type metal-oxide-semiconductor) region; a plurality of fins formed on the substrate; an isolation layer formed between adjacent fins of the plurality of fins and on the substrate; a gate structure across a length portion of the fin and covering a portion of each of a top surface and sidewalls of the fin; and an in-situ doped epitaxial layer formed on each of the etched fin on both sides of the gate structure. The doping ions in the in-situ doped epitaxial layer are N-type ions.

## Claims

### Claim 1

A fin field effect transistor (FinFET), comprising:
a substrate including an NMOS (N-type metal-oxide-semiconductor) region and a PMOS (P-type metal-oxide-semiconductor) region;
a plurality of fins formed on the substrate;
an isolation layer formed between adjacent fins of the plurality of fins and on the substrate;
a gate structure across a length portion of the plurality of fins and covering a portion of each of a top surface and sidewalls of the plurality of fins;
an in-situ doped epitaxial layer formed on one of the plurality of fins on both sides of the gate structure in the NMOS region, wherein doping ions in the in-situ doped epitaxial layer are N-type ions; and
a P-type source-drain doped region formed another one of the plurality of fins on both sides of the gate structure in the PMOS (P-type metal-oxide-semiconductor) region;
wherein a bottom full width of the P-type source-drain doped region is greater than a maximum width of the another one of the plurality of fins in a direction perpendicular to an extension direction of the plurality of fins, and a bottom full width of the in-situ doped epitaxial layer is greater than a maximum width of the one of the plurality of fins in the direction perpendicular to the extension direction of the plurality of fins.

### Claim 2 (depends on 1)

The FinFET according to claim 1, wherein:
the in-situ doped epitaxial layer is made of SiP (Silicon Phosphide) or SiCP (Silicon-Carbon Phosphide).

### Claim 3 (depends on 1)

The FinFET according to claim 1, further including
an etching stop layer formed on the gate structure, the isolation layer, and the in-situ doped epitaxial layer.

### Claim 4 (depends on 3)

The FinFET according to claim 3, further including
an interlayer dielectric layer formed on the etching stop layer.

### Claim 5 (depends on 1)

The FinFET according to claim 1, wherein:
the in-situ doped epitaxial layer has a rectangular bottom section and a round top section.

### Claim 6 (depends on 5)

The FinFET according to claim 5, wherein:
the bottom full width of the rectangular bottom section is greater than 0 nm and less than or equal to 12 nm wider than the maximum width of the one of the plurality of fins in the direction perpendicular to the extension direction of the plurality of fins.

### Claim 7 (depends on 1)

The FinFET according to claim 1, wherein:
the P-type source-drain doped region has a pentagon top with a vertex protruding away from the plurality of fins.

### Claim 8 (depends on 7)

The FinFET according to claim 7, wherein:
a bottom surface of the pentagon top is coplanar with the top surface of the plurality of fins, and
the bottom full width of the bottom surface is wider than the maximum width of the one of the plurality of fins in the direction perpendicular to the extension direction of the plurality of fins.

### Claim 9 (depends on 1)

The FinFET according to claim 1, further including:
an oxidation protection layer formed on surfaces of the P-type source-drain doped region.