# US 11,908,861 B2 · Semiconductor device and method of fabricating the same

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- Number: US 11,908,861 B2
- Document ID: US11908861B2
- Status: Granted
- Kind: B2
- Application number: 17/394,580
- Filed: 2021-08-05
- Published: 2022-06-09
- Granted: 2024-02-20
- Earliest claimed: 2020-12-04
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Munhyeon Kim; Mingyu Kim; Doyoung Choi; Daewon Ha
- Web page: https://patentgrep.com/patent/US11908861B2

## CPC

- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 62/364: {of IGFETs}
- H10D 84/0184: {Manufacturing their gate sidewall spacers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A semiconductor device is disclosed. The semiconductor device may include an active pattern on a substrate, source/drain patterns on the active pattern, a fence spacer on side surfaces of each of the source/drain patterns, a channel pattern interposed between the source/drain patterns, a gate electrode crossing the channel pattern and extending in a first direction, and a gate spacer on a side surface of the gate electrode. A first thickness of an upper portion of the fence spacer in the first direction may be greater than a second thickness of the gate spacer in a second direction crossing the first direction.

## Claims

### Claim 1

A semiconductor device, comprising:
an active pattern on a substrate;
a pair of source/drain patterns on the active pattern;
fence spacers on opposing side surfaces of each of the pair of source/drain patterns;
a channel pattern extending between the pair of source/drain patterns;
a gate electrode crossing the channel pattern and extending in a first direction; and
a gate spacer on a side surface of the gate electrode,
wherein a first thickness of an upper portion of the fence spacers in the first direction is greater than a second thickness of the gate spacer in a second direction crossing the first direction,
wherein the source/drain patterns have a first height, the fence spacers have a second height, and the second height is 50% to 100% of the first height.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the first thickness is about 1.5 to 3 times the second thickness.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the first thickness is about 3 nanometers (nm) to about 12 nm, and the second thickness is about 2 nm to about 6 nm.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the first thickness of the upper portion of the fence spacers is greater than a third thickness of a lower portion of the fence spacers.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the first thickness of the upper portion of the fence spacers is about 1.5 to about 3 times the third thickness of the lower portion.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the fence spacers comprise a second fence portion and a first fence portion between the source/drain patterns and the second fence portion.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein the second fence portion has a nitrogen concentration higher than the first fence portion.

### Claim 8 (depends on 6)

The semiconductor device of claim 6, wherein the second fence portion has a higher density than the first fence portion.

### Claim 9 (depends on 6)

The semiconductor device of claim 6, wherein the first fence portion has substantially a same thickness at upper and lower regions thereof, and the second fence portion is thicker at an upper region thereof than at a lower region thereof.

### Claim 10

A semiconductor device, comprising:
a first active pattern on a first region of a substrate;
a pair of first source/drain patterns on the first active pattern;
first fence spacers on opposing side surfaces of each of the pair of first source/drain patterns;
a first channel pattern extending between the pair of first source/drain patterns;
a first gate electrode crossing the first channel pattern and extending in a first direction; and
a first gate spacer on a side surface of the first gate electrode,
wherein a first thickness of an upper portion of the first fence spacers in the first direction is greater than a third thickness of a lower portion of the first fence spacers in the first direction.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the first fence spacers comprise a second fence portion and a first fence portion between the first source/drain patterns and the second fence portion, and
the second fence portion has a nitrogen concentration higher than the first fence portion.

### Claim 12 (depends on 10)

The semiconductor device of claim 10, wherein the first thickness of the upper portion of the first fence spacers is greater than a second thickness of the first gate spacer in a second direction crossing the first direction.

### Claim 13 (depends on 10)

The semiconductor device of claim 10, wherein the first thickness of the upper portion of the first fence spacers is about 1.5 to 3 times the third thickness of the lower portion of the first fence spacers.

### Claim 14 (depends on 10)

The semiconductor device of claim 10, further comprising:
a second active pattern on a second region of the substrate;
a pair of second source/drain patterns on the second active pattern;
second fence spacers on side surfaces of each of the pair of second source/drain patterns;
a second channel pattern extending between the pair of second source/drain patterns;
a second gate electrode crossing the second channel pattern and extending in the first direction; and
a second gate spacer on a side surface of the second gate electrode.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein the first region is a PMOSFET region,
the second region is an NMOSFET region, and
the first thickness of the upper portion of the first fence spacers is greater than a fourth thickness of an upper portion of the second fence spacers,
wherein the first fence spacers comprise a third fence portion, and wherein the second fence spacers are free of the third fence portion.

### Claim 16 (depends on 14)

The semiconductor device of claim 14, wherein the first region and the second region are of a same conductivity type,
the first channel pattern comprises a plurality of first channel patterns, which are spaced apart from each other with a first pitch in the first direction,
the second channel pattern comprises a plurality of second channel patterns, which are spaced apart from each other with a second pitch, which is smaller than the first pitch, in the first direction, and
the first thickness of the upper portion of the first fence spacers is greater than a fifth thickness of an upper portion of the second fence spacers.

### Claim 17

A semiconductor device, comprising:
an active pattern on a substrate;
a pair of source/drain patterns on the active pattern;
fence spacers on opposing side surfaces of each of the pair of source/drain patterns;
a channel pattern extending between the pair of source/drain patterns;
a gate electrode crossing the channel pattern and extending in a first direction;
a gate insulating layer between the gate electrode and the channel pattern;
a gate spacer on a side surface of the gate electrode;
a gate capping pattern on a top surface of the gate electrode;
a first interlayer insulating layer on the gate capping pattern;
active contacts extending through the first interlayer insulating layer and contacting the source/drain patterns;
gate contacts extending through the first interlayer insulating layer and contacting the gate electrode;
a second interlayer insulating layer on the first interlayer insulating layer;
a first metal layer in the second interlayer insulating layer, the first metal layer comprising first interconnection lines, which are electrically and respectively connected to the active contacts and the gate contacts and extend in a second direction crossing the first direction to be parallel to each other;
a third interlayer insulating layer on the second interlayer insulating layer; and
a second metal layer in the third interlayer insulating layer,
wherein the second metal layer comprises second interconnection lines, which are electrically connected to the first interconnection lines and extend in the first direction to be parallel to each other, and
a first thickness of an upper portion of the fence spacers in the first direction is greater than a second thickness of the gate spacer in the second direction, and is greater than a third thickness of a lower portion of the fence spacers in the first direction.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein the first thickness of the upper portion of the fence spacers is about 1.5 to 3 times the third thickness of the lower portion of the fence spacers.

### Claim 19 (depends on 17)

The semiconductor device of claim 17, wherein the fence spacers comprise a second fence portion and a first fence portion between the source/drain patterns and the second fence portion, and the second fence portion has a nitrogen concentration higher than the first fence portion.