# US 11,908,859 B2 · Semiconductor device including transistors sharing gates with structures having reduced parasitic circuit

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- Number: US 11,908,859 B2
- Document ID: US11908859B2
- Status: Granted
- Kind: B2
- Application number: 17/570,872
- Filed: 2022-01-07
- Published: 2022-04-28
- Granted: 2024-02-20
- Earliest claimed: 2017-08-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Yi-Feng Chang; Po-Lin Peng; Jam-Wem Lee
- Web page: https://patentgrep.com/patent/US11908859B2

## CPC

- H10D 84/854: {comprising arrangements for preventing bipolar actions between the different IGFET regions, e.g. arrangements for latchup prevention}
- H10D 8/80: PNPN diodes, e.g. Shockley diodes or break-over diodes
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 89/713: {including a PNP transistor and a NPN transistor, wherein each of said transistors has its base region coupled to the collector region of the other transistor, e.g. silicon controlled rectifier [SCR] devices}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes a first to sixth regions, a first gate, a first metal contact and a second metal contact. The second region is disposed opposite to the first region with respect to the first gate. The first metal contact couples the first region to the second region. The fourth region is disposed opposite to the third region with respect to the first gate. The second metal contact is coupling the third region to the fourth region. The fifth region is disposed between the first gate and the second region, and is disconnected from the first metal contact and the second metal contact. The sixth region is disposed between the first gate and the first region, and is disconnected from the first metal contact and the second metal contact.

## Claims

### Claim 1

A semiconductor device, comprising:
a first region;
a first gate;
a second region disposed opposite to the first region with respect to the first gate;
a first metal contact coupling the first region to the second region;
a third region;
a fourth region disposed opposite to the third region with respect to the first gate;
a second metal contact coupling the third region to the fourth region;
a fifth region disposed between the first gate and the second region, and disconnected from the first metal contact and the second metal contact; and
a sixth region disposed between the first gate and the first region, and disconnected from the first metal contact and the second metal contact.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising:
a seventh region disposed between the first gate and the second region, and disconnected from the first metal contact and the second metal contact, wherein a type of the fifth region and a type of the seventh region are different.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, further comprising:
a third metal contact configured to couple the fifth region to the seventh region.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, further comprising:
a fourth metal contact configured to receive a current from the sixth region.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, further comprising:
a seventh region disposed between the fifth region and the sixth region, connected with the first metal contact and disconnected from the second metal contact.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, further comprising:
an eighth region disposed between the fifth region and the sixth region, connected with the second metal contact and disconnected from the first metal contact.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, further comprising:
a second gate disposed between the fifth region and the second region; and
a seventh region disposed between the second gate and the second region, and disconnected from the first metal contact and the second metal contact.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, further comprising:
a seventh region disposed between the first region and the sixth region, connected with the first metal contact and disconnected from the second metal contact; and
an eighth region disposed between the first region and seventh sixth region, and disconnected from the first metal contact and the second metal contact.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, further comprising:
a second gate disposed between the eighth region and the first region; and
a third gate disposed between the seventh region and the sixth region.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein the sixth region is disposed between two terminals of the first metal contact, and
the two terminals of the first metal contact are disposed between the first region and the second region.

### Claim 11

A semiconductor device, comprising:
a first metal contact configured to have a first voltage level;
a second metal contact configured to have a second voltage level;
a first gate disposed between two terminals of the first metal contact, and disposed between two terminals of the second metal contact;
a second gate disposed between the first gate and a first terminal of the two terminals of the first metal contact, and disposed between the first gate and a first terminal of the two terminals of the second metal contact; and
a third metal contact disposed between the first gate and the second gate, and disconnected from the first metal contact and the second metal contact.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, further comprising:
a fourth metal contact disposed between the second gate and the first terminal of the first metal contact, and disposed between the second gate and the first terminal of the second metal contact.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, further comprising:
a first region disposed between the second gate and the first terminal of the first metal contact, and coupled to the fourth metal contact; and
a second region disposed between the second gate and the first terminal of the second metal contact, and coupled to the fourth metal contact,
wherein the first region and the second region are different type.

### Claim 14 (depends on 11)

The semiconductor device of claim 11, further comprising:
a first region disposed between the second gate and the first gate, and coupled to the third metal contact; and
a second region opposite to the first region with respect to the first gate, and coupled to the first metal contact.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, further comprising:
a third region disposed between the second gate and the first gate, and coupled to the third metal contact; and
a fourth region opposite to the third region with respect to the first gate, and coupled to the second metal contact,
wherein the first region and the second region are a first type, and the third region and the fourth region are a second type different from the first type.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the first region, the second region and the first gate are configured to operate as a first transistor,
the third region, the fourth region and the first gate are configured to operate as a second transistor, and
a terminal of the first transistor is coupled to a terminal of the second transistor.

### Claim 17

A semiconductor device, comprising:
a first transistor, wherein a first terminal of the first transistor is configured to receive a first voltage signal;
a second transistor, wherein a first terminal of the second transistor is configured to receive a second voltage signal, a second terminal of the second transistor is coupled to a control terminal of the first transistor, and a control terminal of the second transistor is coupled to a second terminal of the first transistor;
a third transistor, wherein a first terminal of the third transistor is configured to receive the first voltage signal; and
a fourth transistor, wherein a first terminal of the fourth transistor is configured to receive the second voltage signal, a second terminal of the fourth transistor is coupled to a second terminal of the third transistor, and a control terminal of the fourth transistor is configured to receive the second voltage signal through a first resistor.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein a control terminal of the fourth transistor is configured to receive the first voltage signal through a second resistor.

### Claim 19 (depends on 17)

The semiconductor device of claim 17, further comprising:
a gate corresponding to a control terminal of the third transistor and the control terminal of the fourth transistor;
a first region corresponding to the first terminal of the third transistor, and disposed at a first side of the gate;
a second region corresponding to the first terminal of the fourth transistor, and disposed at the first side of the gate;
a third region corresponding to the second terminal of the third transistor, and disposed at a second side of the gate; and
a fourth region corresponding to the second terminal of the fourth transistor, and disposed at the second side of the gate.

### Claim 20 (depends on 17)

The semiconductor device of claim 17, further comprising:
a first metal contact configured to receive the first voltage signal and has a U shape; and
a second metal contact configured to receive the second voltage signal and has the U shape,
wherein the third transistor is disposed between two terminals of the first metal contact, and
the fourth transistor is disposed between two terminals of the second metal contact.