# US 11,908,858 B2 · Semiconductor device

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- Number: US 11,908,858 B2
- Document ID: US11908858B2
- Status: Granted
- Kind: B2
- Application number: 16/937,912
- Filed: 2020-07-24
- Published: 2020-11-12
- Granted: 2024-02-20
- Earliest claimed: 2015-11-16
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Sung Soo Kim; Gi Gwan Park; Jung Hun Choi; Koung Min Ryu; Sun Jung Lee
- Web page: https://patentgrep.com/patent/US11908858B2

## CPC

- H10D 84/834: {comprising FinFETs}
- H10D 64/514: {characterised by the insulating layers}
- H10D 64/517: {characterised by the conducting layers}
- H10D 84/0142: {the gate conductors having different shapes or dimensions}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10D 12/211: {Gated diodes}
- H10D 84/8312: {the IGFETs characterised by having different source or drain region structures, e.g. IGFETs having symmetrical source or drain regions integrated with IGFETs having asymmetrical source or drain regions}
- H10D 84/853: {comprising FinFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a substrate including a first region, and a second region, a first gate structure and a second gate structure on the substrate of the first region, a third gate structure and a fourth gate structure on the substrate of the second region, a first interlayer insulating film on the substrate of the first region and including a first lower interlayer insulating film and a first upper interlayer insulating film, a second interlayer insulating film on the substrate of the second region and including a second lower interlayer insulating film and a second upper interlayer insulating film, a first contact between the first gate structure and the second gate structure and within the first interlayer insulating film, and a second contact formed between the third gate structure and the fourth gate structure and within the second interlayer insulating film.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate including a first region and a second region;
a first gate structure and a second gate structure on the substrate of the first region, the first gate structure and the second gate structure being spaced apart by a first distance;
a third gate structure and a fourth gate structure on the substrate of the second region, the third gate structure and the fourth gate structure being spaced apart by a second distance greater than the first distance;
a first liner extending along and contacting a portion of a sidewall of the first gate structure, continuing along and contacting an upper surface of the substrate, and continuing along and contacting a portion of a sidewall of the second gate structure;
a second liner extending along a portion of a sidewall of the third gate structure, the upper surface of the substrate, and a portion of a sidewall of the fourth gate structure;
a first interlayer insulating film on the first liner and surrounding the sidewall of the first gate structure and the sidewall of the second gate structure;
a second interlayer insulating film on the second liner and surrounding the sidewall of the third gate structure and the sidewall of the fourth gate structure;
a first contact between the first gate structure and the second gate structure and within the first interlayer insulating film, the first contact having a first width; and
a second contact between the third gate structure and the fourth gate structure and within the second interlayer insulating film, the second contact having a second width greater than the first width,
the first width being correlated to a width of an upper surface of the first gate structure, and the second width being correlated to a width of an upper surface of the third gate structure.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the first interlayer insulating film includes a first lower interlayer insulating film on the first liner, and a first upper interlayer insulating film on the first lower interlayer insulating film, and
the second interlayer insulating film includes a second lower interlayer insulating film on the second liner, and a second upper interlayer insulating film on the second lower interlayer insulating film.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the first lower interlayer insulating film is not interposed between the first upper interlayer insulating film and the sidewall of the first gate structure, and the first lower interlayer insulating film is not interposed between the first upper interlayer insulating film and the sidewall of the second gate structure, and
the second lower interlayer insulating film is not interposed between the second upper interlayer insulating film and the sidewall of the third gate structure, and the second lower interlayer insulating film is not interposed between the second upper interlayer insulating film and the sidewall of the fourth gate structure.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein a height of an uppermost portion of the first liner on the sidewall of the first gate structure is lower than a height of the upper surface of the first gate structure, and
a height of an uppermost portion of the second liner on the sidewall of the third gate structure is lower than a height of the upper surface of the third gate structure.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein a distance from the upper surface of the first gate structure to an uppermost portion of the first liner is substantially equal to a distance from the upper surface of the third gate structure to an uppermost portion of the second liner.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the first gate structure includes a first gate electrode, and the third gate structure includes a second gate electrode, and
a sign of a slope of a sidewall of the first gate electrode is different from a sign of a slope of a sidewall of the second gate electrode.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein a distance from the upper surface of the first gate structure to an uppermost portion of the first liner is greater than a distance from the upper surface of the third gate structure to an uppermost portion of the second liner.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the first gate structure includes a first gate electrode, and the third gate structure includes a second gate electrode, and
a sign of a slope of a sidewall of the first gate electrode is identical to a sign of a slope of a sidewall of the second gate electrode.

### Claim 9

A semiconductor device, comprising:
a substrate including a first region, and a second region;
a first gate structure and a second gate structure on the substrate of the first region, the first gate structure and the second gate structure being spaced apart by a first distance;
a third gate structure and a fourth gate structure on the substrate of the second region, the third gate structure and the fourth gate structure being spaced apart by a second distance lower than the first distance;
a first liner along and contacting a sidewall of the first gate structure, continuing along and contacting an upper surface of the substrate, and continuing along and contacting a sidewall of the second gate structure, the first liner not being formed on an upper surface of the first gate structure and an upper surface of the second gate structure;
a second liner along a sidewall of the third gate structure, the upper surface of the substrate, and a sidewall of the fourth gate structure, the second liner not being formed on an upper surface of the third gate structure and an upper surface of the fourth gate structure;
a first interlayer insulating film on the first liner and surrounding the sidewall of the first gate structure and the sidewall of the second gate structure;
a second interlayer insulating film on the second liner and surrounding the sidewall of the third gate structure and the sidewall of the fourth gate structure;
a first contact between the first gate structure and the second gate structure and within the first interlayer insulating film, the first contact having a first width; and
a second contact between the third gate structure and the fourth gate structure and within the second interlayer insulating film, the second contact having a second width lower than the first width,
the first width being correlated to a width of the upper surface of the first gate structure, and the second width being correlated to a width of the upper surface of the third gate structure.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the first interlayer insulating film includes a first lower interlayer insulating film, and a first upper interlayer insulating film on the first lower interlayer insulating film, and
the first lower interlayer insulating film is not interposed between the first upper interlayer insulating film and the sidewall of the first gate structure, and the first lower interlayer insulating film is not interposed between the first upper interlayer insulating film and the sidewall of the second gate structure.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the first liner is on a portion of the sidewall of the first gate structure, and a portion of the sidewall of the second gate structure, and
a distance from the upper surface of the substrate to an uppermost portion of the second liner is substantially equal to a distance from the upper surface of the substrate to an upper surface of the third gate structure.

### Claim 12 (depends on 10)

The semiconductor device of claim 10, wherein the second interlayer insulating film includes a second lower interlayer insulating film, and a second upper interlayer insulating film on the second lower interlayer insulating film, and
the second lower interlayer insulating film is not interposed between the second upper interlayer insulating film and the sidewall of the third gate structure, and the second lower interlayer insulating film is not interposed between the second upper interlayer insulating film and the sidewall of the fourth gate structure.

### Claim 13

A semiconductor device, comprising:
a gate structure on a substrate and including a first sidewall and a second sidewall;
a first source/drain adjacent to the first sidewall of the gate structure;
a second source/drain adjacent to the second sidewall of the gate structure;
a liner extending along the first sidewall of the gate structure, the second sidewall of the gate structure, an upper surface of the first source/drain, and an upper surface of the second source/drain; and
a contact contacting the first sidewall of the gate structure and being connected with the first source/drain, a height of the liner on the first sidewall of the gate structure being different from a height of the liner on the second sidewall of the gate structure.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein the height of the liner on the first sidewall of the gate structure is lower than the height of the liner on the second sidewall of the gate structure.

### Claim 15 (depends on 13)

The semiconductor device of claim 13, wherein the liner is on a portion of the first sidewall of the gate structure, and on a portion of the second sidewall of the gate structure.

### Claim 16 (depends on 13)

The semiconductor device of claim 13, the semiconductor device not including a contact contacting the second sidewall of the gate structure and connected with the second source/drain.

### Claim 17 (depends on 13)

The semiconductor device of claim 13, further comprising an interlayer insulating film surrounding the second sidewall of the gate structure, and covering an upper surface of the liner.

### Claim 18 (depends on 13)

The semiconductor device of claim 13, wherein a width of the contact increases as a distance from an upper surface of the substrate increases.

### Claim 19 (depends on 13)

The semiconductor device of claim 13, wherein a width of the contact alternately decreases and increases as a distance between the contact and an upper surface of the substrate increases.

### Claim 20 (depends on 13)

The semiconductor device of claim 13, wherein the gate structure includes a gate spacer defining a trench, and a gate insulating film along a sidewall and a bottom surface of the trench.