# US 11,908,856 B2 · Gate-all-around integrated circuit structures having devices with source/drain-to-substrate electrical contact

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- Number: US 11,908,856 B2
- Document ID: US11908856B2
- Status: Granted
- Kind: B2
- Application number: 16/719,257
- Filed: 2019-12-18
- Published: 2021-06-24
- Granted: 2024-02-20
- Earliest claimed: 2019-12-18
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Biswajeet Guha; William Hsu; Chung-Hsun Lin; Kinyip Phoa; Oleg Golonzka; Tahir Ghani; Kalyan Kolluru; Nathan Jack; Nicholas Thomson; Ayan Kar; Benjamin Orr
- Web page: https://patentgrep.com/patent/US11908856B2

## CPC

- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10D 84/834: {comprising FinFETs}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/01: Manufacture or treatment
- H10D 64/251: {Source or drain electrodes for field-effect devices}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D 84/832: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

Gate-all-around structures having devices with source/drain-to-substrate electrical contact are described. An integrated circuit structure includes a first vertical arrangement of horizontal nanowires above a first fin. A first gate stack is over the first vertical arrangement of horizontal nanowires. A first pair of epitaxial source or drain structures is at first and second ends of the first vertical arrangement of horizontal nanowires. One or both of the first pair of epitaxial source or drain structures is directly electrically coupled to the first fin. A second vertical arrangement of horizontal nanowires is above a second fin. A second gate stack is over the second vertical arrangement of horizontal nanowires. A second pair of epitaxial source or drain structures is at first and second ends of the second vertical arrangement of horizontal nanowires. Both of the second pair of epitaxial source or drain structures is electrically isolated from the second fin.

## Claims

### Claim 1

An integrated circuit structure, comprising:
a first vertical arrangement of horizontal nanowires above a first fin;
a first gate stack over the first vertical arrangement of horizontal nanowires;
a first pair of epitaxial source or drain structures at first and second ends of the first vertical arrangement of horizontal nanowires, one or both of the first pair of epitaxial source or drain structures directly electrically coupled to the first fin;
a second vertical arrangement of horizontal nanowires above a second fin;
a second gate stack over the second vertical arrangement of horizontal nanowires; and
a second pair of epitaxial source or drain structures at first and second ends of the second vertical arrangement of horizontal nanowires, both of the second pair of epitaxial source or drain structures electrically isolated from the second fin, wherein the second pair of epitaxial source or drain structures has a bottommost surface vertically between a bottommost nanowire of the second vertical arrangement of horizontal nanowires and an uppermost surface of the second fin.

### Claim 2 (depends on 1)

The integrated circuit structure of claim 1, wherein the first and second pairs of epitaxial source or drain structures are first and second pairs of non-discrete epitaxial source or drain structures.

### Claim 3 (depends on 1)

The integrated circuit structure of claim 1, wherein the first and second fins each comprises a portion of a bulk silicon substrate.

### Claim 4 (depends on 1)

The integrated circuit structure of claim 1, wherein the nanowires of the first and second vertical arrangements of horizontal nanowires comprise silicon.

### Claim 5 (depends on 4)

The integrated circuit structure of claim 4, wherein the first and second pairs of epitaxial source or drain structures comprise silicon germanium.

### Claim 6 (depends on 1)

The integrated circuit structure of claim 1, wherein the nanowires of the first and second vertical arrangements of horizontal nanowires comprise silicon germanium.

### Claim 7 (depends on 1)

The integrated circuit structure of claim 1, wherein each of the first and second gate stacks comprises a high-k gate dielectric layer and a metal gate electrode.

### Claim 8 (depends on 1)

The integrated circuit structure of claim 1, wherein both of the pair of epitaxial source or drain structures are directly electrically coupled to the first fin, the integrated circuit structure further comprising a trench in the first fin, the trench beneath the first gate stack.

### Claim 9 (depends on 1)

The integrated circuit structure of claim 1, wherein both of the pair of epitaxial source or drain structures are directly electrically coupled to the first fin, the integrated circuit structure further comprising a heavily doped region in the first fin, the heavily doped region beneath the first gate stack.

### Claim 10

An integrated circuit structure, comprising:
a first vertical arrangement of horizontal nanowires above a first fin;
a first gate stack over the first vertical arrangement of horizontal nanowires;
a first pair of epitaxial source or drain structures at first and second ends of the first vertical arrangement of horizontal nanowires, one of the first pair of epitaxial source or drain structures directly electrically coupled to the first fin, and the other of the first pair of epitaxial source or drain structures electrically isolated from the first fin;
a second vertical arrangement of horizontal nanowires above a second fin;
a second gate stack over the second vertical arrangement of horizontal nanowires; and
a second pair of epitaxial source or drain structures at first and second ends of the second vertical arrangement of horizontal nanowires, both of the second pair of epitaxial source or drain structures electrically isolated from the second fin, wherein the second pair of epitaxial source or drain structures has a bottommost surface vertically between a bottommost nanowire of the second vertical arrangement of horizontal nanowires and an uppermost surface of the second fin.

### Claim 11 (depends on 10)

The integrated circuit structure of claim 10, wherein the first and second pairs of epitaxial source or drain structures are first and second pairs of non-discrete epitaxial source or drain structures.

### Claim 12 (depends on 10)

The integrated circuit structure of claim 10, wherein the first and second fins each comprises a portion of a bulk silicon substrate.

### Claim 13 (depends on 10)

The integrated circuit structure of claim 10, wherein the nanowires of the first and second vertical arrangements of horizontal nanowires comprise silicon.

### Claim 14 (depends on 13)

The integrated circuit structure of claim 13, wherein the first and second pairs of epitaxial source or drain structures comprise silicon germanium.

### Claim 15 (depends on 10)

The integrated circuit structure of claim 10, wherein the nanowires of the first and second vertical arrangements of horizontal nanowires comprise silicon germanium.

### Claim 16 (depends on 10)

The integrated circuit structure of claim 10, wherein each of the first and second gate stacks comprises a high-k gate dielectric layer and a metal gate electrode.

### Claim 17

A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a first vertical arrangement of horizontal nanowires above a first fin;
a first gate stack over the first vertical arrangement of horizontal nanowires;
a first pair of epitaxial source or drain structures at first and second ends of the first vertical arrangement of horizontal nanowires, one or both of the pair of epitaxial source or drain structures directly electrically coupled to the first fin;
a second vertical arrangement of horizontal nanowires above a second fin;
a second gate stack over the second vertical arrangement of horizontal nanowires; and
a second pair of epitaxial source or drain structures at first and second ends of the second vertical arrangement of horizontal nanowires, both of the pair of epitaxial source or drain structures electrically isolated from the second fin, wherein the second pair of epitaxial source or drain structures has a bottommost surface vertically between a bottommost nanowire of the second vertical arrangement of horizontal nanowires and an uppermost surface of the second fin.

### Claim 18 (depends on 17)

The computing device of claim 17, further comprising:
a memory coupled to the board.

### Claim 19 (depends on 17)

The computing device of claim 17, further comprising:
a communication chip coupled to the board.

### Claim 20 (depends on 17)

The computing device of claim 17, wherein the component is a packaged integrated circuit die.

### Claim 21 (depends on 17)

The computing device of claim 17, wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

### Claim 22 (depends on 17)

The computing device of claim 17, wherein the computing device is selected from the group consisting of a mobile phone, a laptop, a desk top computer, a server, and a set-top box.