# US 11,908,855 B2 · Semiconductor devices with circuit and external dummy areas

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- Number: US 11,908,855 B2
- Document ID: US11908855B2
- Status: Granted
- Kind: B2
- Application number: 17/880,819
- Filed: 2022-08-04
- Published: 2022-11-24
- Granted: 2024-02-20
- Earliest claimed: 2019-12-10
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Seonah Nam; Byungju Kang; Byungsung Kim; Hyelim Kim; Sungho Park; Yubo Qian
- Web page: https://patentgrep.com/patent/US11908855B2

## CPC

- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 64/511: {for IGFETs}
- H10D 89/10: Integrated device layouts
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/635: {Through-vias}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A semiconductor device includes first and second external dummy areas, and a circuit area between the first and second external dummy areas. The circuit area includes circuit active regions and circuit gate lines. Each external dummy area includes an external dummy active region and external dummy gate lines overlapping the external dummy active region and spaced apart from the circuit gate lines. The external dummy active region has a linear shape extending in a first horizontal direction or a shape including active portions isolated from direct contact with each other and extending sequentially in the first horizontal direction. The circuit active regions are between the first and second external dummy active regions and include a first plurality of circuit active regions extending sequentially in the first horizontal direction and a second plurality of circuit active regions extending sequentially in a second horizontal direction perpendicular to the first horizontal direction.

## Claims

### Claim 1

A semiconductor device, comprising:
a first external dummy area;
a second external dummy area; and
a circuit area between the first external dummy area and the second external dummy area,
wherein the circuit area includes circuit active regions, circuit gate lines, and circuit source/drain regions,
wherein the first external dummy area includes a first external dummy active region, and first external dummy gate lines overlapping the first external dummy active region in a vertical direction, the first external dummy gate lines spaced apart from the circuit gate lines,
wherein the second external dummy area includes a second external dummy active region and second external dummy gate lines overlapping the second external dummy active region in the vertical direction, the second external dummy gate lines spaced apart from the circuit gate lines,
wherein each dummy active region of the first external dummy active region and the second external dummy active region has
a linear shape extending in a first horizontal direction, or
a shape including active portions isolated from direct contact with each other and extending sequentially in the first horizontal direction,
wherein the circuit active regions are between the first external dummy active region and the second external dummy active region, and
wherein the circuit active regions include
a first plurality of circuit active regions extending sequentially in the first horizontal direction, and
a second plurality of circuit active regions extending sequentially in a second horizontal direction perpendicular to the first horizontal direction,
wherein each circuit active region of the circuit active regions includes a circuit active pattern and circuit active layers on the circuit active pattern, the circuit active layers spaced apart from each other in the vertical direction and adjacent to the circuit source/drain regions,
wherein the first external dummy active region includes a dummy active pattern and dummy active layers on the dummy active pattern, the dummy active layers spaced apart from each other in the vertical direction,
wherein at least one circuit gate line of the circuit gate lines extends in the second horizontal direction to cover an upper surface, a bottom surface and a side surface of each circuit active layer of the circuit active layers, and
wherein at least one first external dummy gate line of the first external dummy gate lines extends in the second horizontal direction to cover an upper surface, a bottom surface and a side surface of each dummy active layer of the dummy active layers.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising:
a first gate cut insulation region between the first external dummy area and the circuit area; and
a second gate cut insulation region between the second external dummy area and the circuit area,
wherein the first gate cut insulation region includes first gate cut patterns between the circuit gate lines and the first external dummy gate lines, and
wherein the second gate cut insulation region includes second gate cut patterns between the circuit gate lines and the second external dummy gate lines.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein
the first external dummy area further includes first edge gate lines,
the first external dummy gate lines are between the first edge gate lines and the circuit gate lines,
the first external dummy gate lines have a shape of lines or bars parallel to each other, and
at least portions of the first edge gate lines are “U” shaped.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein the first external dummy area further comprises first edge cut patterns between the first edge gate lines and the first external dummy gate lines to isolate the first edge gate lines and the first external dummy gate lines from direct contact with each other.

### Claim 5 (depends on 3)

The semiconductor device of claim 3, wherein when viewed in plan view, the first edge gate lines and the first external dummy gate lines are part of a single, continuous piece of material.

### Claim 6 (depends on 3)

The semiconductor device of claim 3, wherein
the first external dummy active region includes the active portions isolated from direct contact with each other while extending sequentially in the first horizontal direction,
each active portion of the active portions has a shape of a line or a bar extending in the first horizontal direction, and
the circuit active regions include active regions extending sequentially in the first horizontal direction while facing the active portions of the first external dummy active region.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein
the circuit active regions include a first side circuit active region and a second side circuit active region, the first side circuit active region and the second side circuit active region both adjacent to the first external dummy active region,
a distance between the first external dummy active region and the first side circuit active region is less than a distance between the first external dummy active region and the second side circuit active region, and
other circuit active regions of the circuit active regions are not between the first external dummy active region and the first side circuit active region and are not between the first external dummy active region and the second side circuit active region.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, further comprising:
first gate cut patterns isolating the circuit gate lines and the first external dummy gate lines from direct contact with each other, the first gate cut patterns between the circuit gate lines and the first external dummy gate lines,
wherein the first external dummy area further includes first edge cut patterns,
wherein the first external dummy gate lines are between the first edge cut patterns and the first gate cut patterns,
wherein the first gate cut patterns and the first edge cut patterns include a same insulating material,
wherein the first external dummy gate lines have a shape of lines or bars parallel to each other, and
wherein at least portions of the first edge cut patterns have a “U” shape.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein
the circuit area further includes an internal dummy active region,
the circuit active regions are spaced apart from each other in the first horizontal direction,
the circuit active regions include a first circuit active region and a second circuit active region isolated from direct contact with each other by a distance greater than an allowable distance range,
among the circuit active regions arranged in the first horizontal direction, remaining circuit active regions except for the first and second circuit active regions are isolated from direct contact with each other by the allowable distance range, and
the internal dummy active region is between the first circuit active region and the second circuit active region.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein a distance between the first circuit active region and the internal dummy active region, and a distance between the second circuit active region and the internal dummy active region, are each within the allowable distance range.

### Claim 11 (depends on 1)

The semiconductor device of claim 1,
wherein the circuit area further includes:
a circuit contact plug on the circuit source/drain regions, such that the circuit contact plug is configured to be electrically connected to the circuit source/drain regions;
a circuit via on the circuit contact plug, such that the circuit via is configured to be electrically connected to the circuit contact plug; and
a circuit wiring electrically connected to the circuit via,
wherein the first external dummy area further includes
dummy source/drain regions adjacent to the dummy active layers, and
a dummy wiring overlapping the dummy source/drain regions and located at a same height level as the circuit wiring.

### Claim 12 (depends on 11)

The semiconductor device of claim 11,
wherein the first external dummy area further includes the dummy source/drain regions adjacent to the dummy active layers,
wherein the first external dummy area further includes one of
a dummy contact plug and not a dummy via, such that the dummy contact plug is electrically connected to the dummy source/drain regions and is electrically insulated from the dummy wiring, or
a dummy via and not a dummy contact plug, such that the dummy via is electrically insulated from the dummy source/drain regions and is electrically connected to the dummy wiring.

### Claim 13 (depends on 1)

The semiconductor device of claim 1,
wherein the circuit area further includes:
a circuit contact plug on the circuit source/drain regions, such that the circuit contact plug is configured to be electrically connected to the circuit source/drain regions;
a circuit via on the circuit contact plug, such that the circuit via is configured to be electrically connected to the circuit contact plug; and
a circuit wiring electrically connected to the circuit via,
wherein the first external dummy area further includes dummy source/drain regions adjacent to the dummy active layers,
wherein the first external dummy area further includes one of
a dummy contact plug and not a dummy via, such that the dummy contact plug is electrically connected to the dummy source/drain regions, or
a dummy via and not a dummy contact plug, such that the dummy via is electrically insulated from the dummy source/drain regions.

### Claim 14 (depends on 1)

The semiconductor device of claim 1, wherein at least one external dummy active region of the first external dummy active region or the second external dummy active region extends farther in the first horizontal direction than an end of a particular circuit active region that is a last circuit active region among the circuit active regions extending sequentially in the first horizontal direction.

### Claim 15

A semiconductor device, comprising:
a circuit area; and
an external dummy area adjacent the circuit area,
wherein the circuit area includes circuit active regions, circuit gate lines overlapping the circuit active regions in a vertical direction, and circuit source/drain regions,
wherein the external dummy area includes an external dummy active region, external dummy gate lines overlapping the external dummy active region in the vertical direction, and edge gate lines, the external dummy gate lines located between the edge gate lines and the circuit gate lines and isolated from direct contact with the circuit gate lines, wherein the external dummy active region has
a linear shape extending in a first horizontal direction, or
a shape including active portions isolated from direct contact with each other and extending sequentially in the first horizontal direction,
wherein the external dummy gate lines have a shape of lines of bars parallel to each other,
wherein at least portions of the edge gate lines are “U” shaped,
wherein the circuit active regions include
a first plurality of circuit active regions extending sequentially in the first horizontal direction, and
a second plurality of circuit active regions extending sequentially in a second horizontal direction perpendicular to the first horizontal direction,
wherein each circuit active region of the circuit active regions includes a circuit active pattern and circuit active layers on the circuit active pattern, the circuit active layers spaced apart from each other in the vertical direction and adjacent to the circuit source/drain regions, and
wherein the external dummy active region includes a dummy active pattern and dummy active layers on the dummy active pattern, the dummy active layers spaced apart from each other in the vertical direction.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein at least one circuit gate line of the circuit gate lines extends in the second horizontal direction to cover an upper surface, a bottom surface and a side surface of each circuit active layer of the circuit active layers, and
at least one external dummy gate line of the external dummy gate lines extends in the second horizontal direction to cover an upper surface, a bottom surface and a side surface of each dummy active layer of the dummy active layers.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, further comprising a gate cut insulation region between the circuit area and the external dummy area,
wherein the gate cut insulation region includes gate cut patterns between the circuit gate lines and the external dummy gate lines and isolating the circuit gate lines and the external dummy gate lines from direct contact with each other, and
wherein the gate cut patterns extend sequentially in the first horizontal direction.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein the edge gate lines formed of a same material as a material of the external dummy gate lines.

### Claim 19

A semiconductor device, comprising:
a circuit area; and
an external dummy area adjacent to the circuit area,
wherein the circuit area includes circuit active regions, circuit gate lines overlapping the circuit active regions in a vertical direction, and circuit source/drain regions,
wherein the external dummy area includes an external dummy active region, and external dummy gate lines overlapping the external dummy active region in the vertical direction, the external dummy gate lines isolated from direct contact with the circuit gate lines, wherein the external dummy active region has
a linear shape extending in a first horizontal direction, or
a shape including active portions isolated from direct contact with each other and extending sequentially in the first horizontal direction,
wherein the circuit active regions include
a first plurality of circuit active regions extending sequentially in the first horizontal direction, and
a second plurality of circuit active regions extending sequentially in a second horizontal direction perpendicular to the first horizontal direction,
wherein each circuit active region of the circuit active regions includes a circuit active pattern and a circuit channel region on the circuit active pattern and adjacent to the circuit source/drain regions,
wherein the external dummy active region includes a dummy active pattern and a dummy channel region on the dummy active pattern,
wherein at least one circuit gate line of the circuit gate lines covers an upper surface and a side surface of the circuit channel region, and
wherein at least one external dummy gate line of the external dummy gate lines covers an upper surface and a side surface of the dummy channel region.

### Claim 20 (depends on 19)

The semiconductor device of claim 19, wherein
the external dummy area further includes edge gate lines,
the external dummy gate lines are between the edge gate lines and the circuit gate lines,
the external dummy gate lines have a shape of lines or bars parallel to each other, and
at least portions of the edge gate lines are “U” shaped.